if (!surf)
return NULL;
+ assert(ctx->screen->get_param(ctx->screen,
+ PIPE_CAP_DEST_SURFACE_SRGB_CONTROL) ||
+ (util_format_is_srgb(templ->format) ==
+ util_format_is_srgb(resource->format)));
+
res->clean = FALSE;
handle = virgl_object_assign_handle();
pipe_reference_init(&surf->base.reference, 1);
struct virgl_resource *dres = virgl_resource(blit->dst.resource);
struct virgl_resource *sres = virgl_resource(blit->src.resource);
+ assert(ctx->screen->get_param(ctx->screen,
+ PIPE_CAP_DEST_SURFACE_SRGB_CONTROL) ||
+ (util_format_is_srgb(blit->dst.resource->format) ==
+ util_format_is_srgb(blit->dst.format)));
+
dres->clean = FALSE;
virgl_encode_blit(vctx, dres, sres,
blit);
#define VIRGL_CAP_TEXTURE_BARRIER (1 << 12)
#define VIRGL_CAP_TGSI_COMPONENTS (1 << 13)
#define VIRGL_CAP_GUEST_MAY_INIT_LOG (1 << 14)
+#define VIRGL_CAP_SRGB_WRITE_CONTROL (1 << 15)
/* virgl bind flags - these are compatible with mesa 10.5 gallium.
* but are fixed, no other should be passed to virgl either.
return 0;
case PIPE_CAP_NATIVE_FENCE_FD:
return vscreen->vws->supports_fences;
+ case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
+ return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL;
default:
return u_pipe_screen_get_param_defaults(screen, param);
}