radeonsi: flush TC L2 cache for indirect draw data

This fixes a bug when indirect draw data is generated by transform
feedback.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 224cf3513c8b3155c3617394fb1b7ef8fd248b03..7600671d07e31ed1414f55c9cd1f0d4f7d349cba 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1242,10 +1242,10 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
                 * and most other clients can use TC L2 as well, we don't need
                 * to flush it.
                 *
-                * The only case which requires flushing it is VGT DMA index
-                * fetching, which is a rare case. Thus, flag the TC L2
-                * dirtiness in the resource and handle it when index fetching
-                * is used.
+                * The only cases which requires flushing it is VGT DMA index
+                * fetching (on <= CIK) and indirect draw data, which are rare
+                * cases. Thus, flag the TC L2 dirtiness in the resource and
+                * handle it at draw call time.
                 */
                for (i = 0; i < sctx->b.streamout.num_targets; i++)
                        if (sctx->b.streamout.targets[i])

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index a60723d225d1e083f3d6bb5e5c7ca618823afaaf..b55930641315c8533e69eb0e699d8ffc0de35277 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -967,6 +967,11 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
                r600_resource(ib.buffer)->TC_L2_dirty = false;
        }
 
+       if (info->indirect && r600_resource(info->indirect)->TC_L2_dirty) {
+               sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
+               r600_resource(info->indirect)->TC_L2_dirty = false;
+       }
+
        /* Check flush flags. */
        if (sctx->b.flags)
                si_mark_atom_dirty(sctx, sctx->atoms.s.cache_flush);