Cleaned tests

diff --git a/tests/efinix/fsm.v b/tests/efinix/fsm.v
index 0605bd102ddd727902c9714bfe768abd4ab83f5b..368fbaace5e8a1e87b98b937646cc700f049c241 100644 (file)
--- a/tests/efinix/fsm.v
+++ b/tests/efinix/fsm.v
@@ -52,22 +52,4 @@
  endcase\r
  end\r
 \r
- endmodule\r
-\r
- module top (\r
-input clk,\r
-input rst,\r
-input a,\r
-input b,\r
-output g0,\r
-output g1\r
-);\r
-\r
-fsm u_fsm ( .clock(clk),\r
-            .reset(rst),\r
-            .req_0(a),\r
-            .req_1(b),\r
-            .gnt_0(g0),\r
-            .gnt_1(g1));\r
-\r
 endmodule\r

diff --git a/tests/efinix/fsm.ys b/tests/efinix/fsm.ys
index 9de6aa2805dfa2f04f083485715a5277d5e51bfb..2ec75215dbab0125ba2fa86ffde11bab2cc93938 100644 (file)
--- a/tests/efinix/fsm.ys
+++ b/tests/efinix/fsm.ys
@@ -1,12 +1,12 @@
 read_verilog fsm.v
-hierarchy -top top
+hierarchy -top fsm
 proc
 flatten
 #ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'.
 #equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
 equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd fsm # Constrain all select calls below inside the top module
 
 select -assert-count 1  t:EFX_GBUFCE
 select -assert-count 6  t:EFX_FF

diff --git a/tests/efinix/shifter.v b/tests/efinix/shifter.v
index c55632552a4c36f647143cf7ef51cbeec87acf94..ce2c81dd21242a637397854a5f0b8abe033067d4 100644 (file)
--- a/tests/efinix/shifter.v
+++ b/tests/efinix/shifter.v
@@ -9,14 +9,8 @@ in
 \r
     always @(posedge clk)\r
        begin\r
-`ifndef BUG\r
-               out    <= out >> 1;\r
-               out[7] <= in;\r
-`else\r
-\r
                out    <= out << 1;\r
                out[7] <= in;\r
-`endif\r
        end\r
 \r
 endmodule\r

diff --git a/tests/efinix/tribuf.v b/tests/efinix/tribuf.v
index 3fa6eb6c62134f5454cf90769a6b3389288a0d4e..c6446825342680e9b587ad1453b53aad4cbff0a4 100644 (file)
--- a/tests/efinix/tribuf.v
+++ b/tests/efinix/tribuf.v
@@ -2,28 +2,7 @@ module tristate (en, i, o);
     input en;
     input i;
     output reg o;
-`ifndef BUG 
     
     always @(en or i)
                o <= (en)? i : 1'bZ;
-`else
-       
-    always @(en or i)
-               o <= (en)? ~i : 1'bZ;
-`endif
-endmodule
-
-
-module top (
-input en,
-input a,
-output b
-);
-
-tristate u_tri (
-        .en (en ),
-        .i (a ),
-        .o (b )
-    );
-
 endmodule

diff --git a/tests/efinix/tribuf.ys b/tests/efinix/tribuf.ys
index 20d4f215d127b3c078687fb409aeb50fde824666..2e2ab9e653411204e8b104fc2bb7e29cf0d283d9 100644 (file)
--- a/tests/efinix/tribuf.ys
+++ b/tests/efinix/tribuf.ys
@@ -1,12 +1,12 @@
 read_verilog tribuf.v
-hierarchy -top top
+hierarchy -top tristate
 proc
 tribuf
 flatten
 synth
 equiv_opt -assert -map +/efinix/cells_sim.v -map +/simcells.v synth_efinix # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd tristate # Constrain all select calls below inside the top module
 #Internal cell type used. Need support it.
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D