RISC-V: Mention -mbig-endian and -mlittle-endian in doc
authorMarcus Comstedt <marcus@mc.pp.se>
Tue, 5 Jan 2021 21:50:37 +0000 (22:50 +0100)
committerNelson Chu <nelson.chu@sifive.com>
Wed, 6 Jan 2021 10:08:20 +0000 (18:08 +0800)
gas/
    * doc/as.texi: Add -mlittle-endian and -mbig-endian to docs.
    * doc/c-riscv.texi: Likewise.

gas/ChangeLog
gas/doc/as.texi
gas/doc/c-riscv.texi

index 4c500edaa87af525356b27ab1e6b6d9064a6d000..33e6e3e66e0b9380ac910abdb5d8b07925ad3da1 100644 (file)
@@ -1,3 +1,8 @@
+2021-01-06  Marcus Comstedt  <marcus@mc.pp.se>
+
+       * doc/as.texi: Add -mlittle-endian and -mbig-endian to docs.
+       * doc/c-riscv.texi: Likewise.
+
 2021-01-06  Marcus Comstedt  <marcus@mc.pp.se>
 
        * testsuite/gas/riscv/li32.d: Accept bigriscv in addition
index ac45967af8f42acbb571b2cfa61e83fc694fec6a..cf3597f89831e4905d0001ea4bbfca6746c4b11e 100644 (file)
@@ -536,6 +536,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-fpic}|@b{-fPIC}|@b{-fno-pic}]
    [@b{-march}=@var{ISA}]
    [@b{-mabi}=@var{ABI}]
+   [@b{-mlittle-endian}|@b{-mbig-endian}]
 @end ifset
 @ifset RL78
 
index eedd83129e93263bf0240717cc60b92beaf53583..e945482b30f3df9f90af01e09d45a839cdacdb98 100644 (file)
@@ -99,6 +99,14 @@ read-only CSR can not be written by the CSR instructions.
 @cindex @samp{-mno-csr-check} option, RISC-V
 @item -mno-csr-check
 Don't do CSR checking.
+
+@cindex @samp{-mlittle-endian} option, RISC-V
+@item -mlittle-endian
+Generate code for a little endian machine.
+
+@cindex @samp{-mbig-endian} option, RISC-V
+@item -mbig-endian
+Generate code for a big endian machine.
 @end table
 @c man end