[ARM] Enable conditional Armv8-M instructions

Newly introduced instructions common to ARMv8-M Baseline and Mainline
are currently all marked as unconditional. However, all instructions but
sg (ie. blxns, bxns, tt, ttt, tta, ttat, vlldm and vlstm) do actually
support conditional execution. This patch fixes the definition of these
instructions accordingly.

2018-01-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.c (insns): Make blxns, bxns, tt, ttt, tta, ttat, vlldm
	and vlstm conditionally executable and reindent parameters.
	* testsuite/gas/arm/archv8m-cmse-main.s: Add conditional version of
	aforementionned instructions.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 391912c0e2dd79862c980596ed9d6c2fc0111213..53a7e06884932255ff7dcdb7224d52aa278e6a6f 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2018-01-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+       * config/tc-arm.c (insns): Make blxns, bxns, tt, ttt, tta, ttat, vlldm
+       and vlstm conditionally executable and reindent parameters.
+       * testsuite/gas/arm/archv8m-cmse-main.s: Add conditional version of
+       aforementionned instructions.
+
 2018-01-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 
        * config/tc-arm.c (it_fsm_post_encode): Do not warn if targeting M

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index c07362ae7d758b2da8d79af4c17ddc6af338a6bf..925d9947b462b3d39837c92afbd28f9d250fff7e 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -21456,20 +21456,20 @@ static const struct asm_opcode insns[] =
 #define ARM_VARIANT NULL
 #undef  THUMB_VARIANT
 #define THUMB_VARIANT & arm_ext_v8m
- TUE("sg", 0, e97fe97f, 0, (), 0, noargs),
- TUE("blxns", 0, 4784, 1, (RRnpc), 0, t_blx),
- TUE("bxns", 0, 4704, 1, (RRnpc), 0, t_bx),
- TUE("tt", 0, e840f000, 2, (RRnpc, RRnpc), 0, tt),
- TUE("ttt", 0, e840f040, 2, (RRnpc, RRnpc), 0, tt),
- TUE("tta", 0, e840f080, 2, (RRnpc, RRnpc), 0, tt),
- TUE("ttat", 0, e840f0c0, 2, (RRnpc, RRnpc), 0, tt),
+ TUE("sg",    0, e97fe97f, 0, (),            0, noargs),
+ TCE("blxns", 0, 4784,    1, (RRnpc),        0, t_blx),
+ TCE("bxns",  0, 4704,    1, (RRnpc),        0, t_bx),
+ TCE("tt",    0, e840f000, 2, (RRnpc, RRnpc), 0, tt),
+ TCE("ttt",   0, e840f040, 2, (RRnpc, RRnpc), 0, tt),
+ TCE("tta",   0, e840f080, 2, (RRnpc, RRnpc), 0, tt),
+ TCE("ttat",  0, e840f0c0, 2, (RRnpc, RRnpc), 0, tt),
 
  /* FP for ARMv8-M Mainline.  Enabled for ARMv8-M Mainline because the
     instructions behave as nop if no VFP is present.  */
 #undef  THUMB_VARIANT
 #define THUMB_VARIANT & arm_ext_v8m_main
- TUEc("vlldm", 0,       ec300a00, 1, (RRnpc),  rn),
- TUEc("vlstm", 0,       ec200a00, 1, (RRnpc),  rn),
+ TCE("vlldm", 0, ec300a00, 1, (RRnpc), 0, rn),
+ TCE("vlstm", 0, ec200a00, 1, (RRnpc), 0, rn),
 };
 #undef ARM_VARIANT
 #undef THUMB_VARIANT

diff --git a/gas/testsuite/gas/arm/archv8m-cmse-main.s b/gas/testsuite/gas/arm/archv8m-cmse-main.s
index 871414fd19fe6fcd95284e2f7089275c696b716a..4f7ff5d9b1b22b35a49403f3795ce7bde0b5c023 100644 (file)
--- a/gas/testsuite/gas/arm/archv8m-cmse-main.s
+++ b/gas/testsuite/gas/arm/archv8m-cmse-main.s
@@ -2,5 +2,14 @@
 .syntax unified
 
 T:
-vlldm r1
-vlstm r2
+vlldm  r1
+vlstm  r2
+it     ne
+blxnsne        r4
+it     ne
+bxnsne r4
+itttt  ne
+ttane  r0, r1
+ttane  r8, r9
+ttatne r0, r1
+ttatne r8, r9