Add rewrite_sigspecs2, Improve remove() wires

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 79ff4a6a67d05174c947e38e42dcd2f7852d555e..790ba52a30f70b61ab2e4ed864b13bd90e1975c7 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1514,7 +1514,10 @@ void RTLIL::Module::add(RTLIL::Cell *cell)
        cell->module = this;
 }
 
-namespace {
+void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
+{
+       log_assert(refcount_wires_ == 0);
+
        struct DeleteWireWorker
        {
                RTLIL::Module *module;
@@ -1529,17 +1532,29 @@ namespace {
                                }
                        sig = chunks;
                }
-       };
-}
 
-void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
-{
-       log_assert(refcount_wires_ == 0);
+               void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
+                       log_assert(GetSize(lhs) == GetSize(rhs));
+                       RTLIL::SigSpec new_lhs, new_rhs;
+                       for (int i = 0; i < GetSize(lhs); i++) {
+                               RTLIL::SigBit lhs_bit = lhs[i];
+                               if (lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire))
+                                       continue;
+                               RTLIL::SigBit rhs_bit = rhs[i];
+                               if (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))
+                                       continue;
+                               new_lhs.append(lhs_bit);
+                               new_rhs.append(rhs_bit);
+                       }
+                       lhs = new_lhs;
+                       rhs = new_rhs;
+               }
+       };
 
        DeleteWireWorker delete_wire_worker;
        delete_wire_worker.module = this;
        delete_wire_worker.wires_p = &wires;
-       rewrite_sigspecs(delete_wire_worker);
+       rewrite_sigspecs2(delete_wire_worker);
 
        for (auto &it : wires) {
                log_assert(wires_.count(it->name) != 0);

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index a0270bd1cc7ed5d48f0da67589cdbc2bec87ec72..81ca93dce4d1848065e73f41627076a9fb2d73ae 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1001,6 +1001,7 @@ public:
        void fixup_ports();
 
        template<typename T> void rewrite_sigspecs(T &functor);
+       template<typename T> void rewrite_sigspecs2(T &functor);
        void cloneInto(RTLIL::Module *new_mod) const;
        virtual RTLIL::Module *clone() const;
 
@@ -1306,6 +1307,7 @@ public:
        }
 
        template<typename T> void rewrite_sigspecs(T &functor);
+       template<typename T> void rewrite_sigspecs2(T &functor);
 
 #ifdef WITH_PYTHON
        static std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);
@@ -1324,6 +1326,7 @@ struct RTLIL::CaseRule
        bool empty() const;
 
        template<typename T> void rewrite_sigspecs(T &functor);
+       template<typename T> void rewrite_sigspecs2(T &functor);
        RTLIL::CaseRule *clone() const;
 };
 
@@ -1337,6 +1340,7 @@ struct RTLIL::SwitchRule : public RTLIL::AttrObject
        bool empty() const;
 
        template<typename T> void rewrite_sigspecs(T &functor);
+       template<typename T> void rewrite_sigspecs2(T &functor);
        RTLIL::SwitchRule *clone() const;
 };
 
@@ -1347,6 +1351,7 @@ struct RTLIL::SyncRule
        std::vector<RTLIL::SigSig> actions;
 
        template<typename T> void rewrite_sigspecs(T &functor);
+       template<typename T> void rewrite_sigspecs2(T &functor);
        RTLIL::SyncRule *clone() const;
 };
 
@@ -1359,6 +1364,7 @@ struct RTLIL::Process : public RTLIL::AttrObject
        ~Process();
 
        template<typename T> void rewrite_sigspecs(T &functor);
+       template<typename T> void rewrite_sigspecs2(T &functor);
        RTLIL::Process *clone() const;
 };
 
@@ -1420,12 +1426,30 @@ void RTLIL::Module::rewrite_sigspecs(T &functor)
        }
 }
 
+template<typename T>
+void RTLIL::Module::rewrite_sigspecs2(T &functor)
+{
+       for (auto &it : cells_)
+               it.second->rewrite_sigspecs2(functor);
+       for (auto &it : processes)
+               it.second->rewrite_sigspecs2(functor);
+       for (auto &it : connections_) {
+               functor(it.first, it.second);
+       }
+}
+
 template<typename T>
 void RTLIL::Cell::rewrite_sigspecs(T &functor) {
        for (auto &it : connections_)
                functor(it.second);
 }
 
+template<typename T>
+void RTLIL::Cell::rewrite_sigspecs2(T &functor) {
+       for (auto &it : connections_)
+               functor(it.second);
+}
+
 template<typename T>
 void RTLIL::CaseRule::rewrite_sigspecs(T &functor) {
        for (auto &it : compare)
@@ -1438,6 +1462,17 @@ void RTLIL::CaseRule::rewrite_sigspecs(T &functor) {
                it->rewrite_sigspecs(functor);
 }
 
+template<typename T>
+void RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {
+       for (auto &it : compare)
+               functor(it);
+       for (auto &it : actions) {
+               functor(it.first, it.second);
+       }
+       for (auto it : switches)
+               it->rewrite_sigspecs2(functor);
+}
+
 template<typename T>
 void RTLIL::SwitchRule::rewrite_sigspecs(T &functor)
 {
@@ -1446,6 +1481,14 @@ void RTLIL::SwitchRule::rewrite_sigspecs(T &functor)
                it->rewrite_sigspecs(functor);
 }
 
+template<typename T>
+void RTLIL::SwitchRule::rewrite_sigspecs2(T &functor)
+{
+       functor(signal);
+       for (auto it : cases)
+               it->rewrite_sigspecs2(functor);
+}
+
 template<typename T>
 void RTLIL::SyncRule::rewrite_sigspecs(T &functor)
 {
@@ -1456,6 +1499,15 @@ void RTLIL::SyncRule::rewrite_sigspecs(T &functor)
        }
 }
 
+template<typename T>
+void RTLIL::SyncRule::rewrite_sigspecs2(T &functor)
+{
+       functor(signal);
+       for (auto &it : actions) {
+               functor(it.first, it.second);
+       }
+}
+
 template<typename T>
 void RTLIL::Process::rewrite_sigspecs(T &functor)
 {
@@ -1464,6 +1516,14 @@ void RTLIL::Process::rewrite_sigspecs(T &functor)
                it->rewrite_sigspecs(functor);
 }
 
+template<typename T>
+void RTLIL::Process::rewrite_sigspecs2(T &functor)
+{
+       root_case.rewrite_sigspecs2(functor);
+       for (auto it : syncs)
+               it->rewrite_sigspecs2(functor);
+}
+
 YOSYS_NAMESPACE_END
 
 #endif