unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
unsigned dma_flags = tc_l2_flag;
- si_need_cs_space(sctx, 7 + (sctx->b.flags ? sctx->cache_flush.num_dw : 0),
- FALSE);
+ si_need_cs_space(sctx);
/* This must be done after need_cs_space. */
radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
unsigned sync_flags = tc_l2_flag;
unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
- si_need_cs_space(sctx, 7 + (sctx->b.flags ? sctx->cache_flush.num_dw : 0), FALSE);
+ si_need_cs_space(sctx);
/* Flush the caches for the first copy only. Also wait for old CP DMA packets to complete. */
if (sctx->b.flags) {
#include "si_pipe.h"
/* initialize */
-void si_need_cs_space(struct si_context *ctx, unsigned num_dw,
- boolean count_draw_in)
+void si_need_cs_space(struct si_context *ctx)
{
struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs;
void si_context_gfx_flush(void *context, unsigned flags,
struct pipe_fence_handle **fence);
void si_begin_new_cs(struct si_context *ctx);
-void si_need_cs_space(struct si_context *ctx, unsigned num_dw, boolean count_draw_in);
+void si_need_cs_space(struct si_context *ctx);
/* si_compute.c */
void si_init_compute_functions(struct si_context *sctx);
static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
bool include_draw_vbo)
{
- si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
+ si_need_cs_space((struct si_context*)ctx);
}
static void si_init_config(struct si_context *sctx);
if (sctx->b.flags)
si_mark_atom_dirty(sctx, sctx->atoms.s.cache_flush);
- si_need_cs_space(sctx, 0, TRUE);
+ si_need_cs_space(sctx);
/* Emit states. */
mask = sctx->dirty_atoms;