SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim...

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 7853160e21ec8143f578da37bac725d8cd93f856..9139749c08aff791f611102fe760103c73746dc8 100644 (file)
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -45,9 +45,9 @@ struct BtorDumperConfig
 struct WireInfo
 {
        RTLIL::IdString cell_name;
-       RTLIL::SigChunk *chunk;
+       const RTLIL::SigChunk *chunk;
 
-       WireInfo(RTLIL::IdString c, RTLIL::SigChunk* ch) : cell_name(c), chunk(ch) { }
+       WireInfo(RTLIL::IdString c, const RTLIL::SigChunk* ch) : cell_name(c), chunk(ch) { }
 };
 
 struct WireInfoOrder

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 4b60f0fbdfae2bc1a2fe3d4d3e21c12895e0b3cd..1608350871523b356412be4b7b20a36b0273ab9c 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -149,7 +149,7 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
        return true;
 }
 
-void dump_const(FILE *f, RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool set_signed = false)
+void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool set_signed = false)
 {
        if (width < 0)
                width = data.bits.size() - offset;
@@ -203,7 +203,7 @@ void dump_const(FILE *f, RTLIL::Const &data, int width = -1, int offset = 0, boo
        }
 }
 
-void dump_sigchunk(FILE *f, RTLIL::SigChunk &chunk, bool no_decimal = false)
+void dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool no_decimal = false)
 {
        if (chunk.wire == NULL) {
                dump_const(f, chunk.data, chunk.width, chunk.offset, no_decimal);

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 34a3f1ba94426e3451b69558814382aba6259ac9..a51064c3ecf2c605b821617de2bc7d66de45a87f 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -311,7 +311,7 @@ struct AST_INTERNAL::ProcessGenerator
                sig.optimize();
                for (size_t i = 0; i < sig.chunks().size(); i++)
                {
-                       RTLIL::SigChunk &chunk = sig.chunks()[i];
+                       RTLIL::SigChunk &chunk = sig.chunks_rw()[i];
                        if (chunk.wire == NULL)
                                continue;
 

diff --git a/kernel/consteval.h b/kernel/consteval.h
index 564098c6a78ca01b13db4fa0544a299445ca5041..5836cdd5b9448e8fe67c99f3c0026e02e44ea92d 100644 (file)
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -73,7 +73,7 @@ struct ConstEval
                RTLIL::SigSpec current_val = values_map(sig);
                current_val.expand();
                for (size_t i = 0; i < current_val.chunks().size(); i++) {
-                       RTLIL::SigChunk &chunk = current_val.chunks()[i];
+                       const RTLIL::SigChunk &chunk = current_val.chunks()[i];
                        assert(chunk.wire != NULL || chunk.data.bits[0] == value.bits[i]);
                }
 #endif

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 43511304e1776378799d23d261ccec3f6bd929b9..361cd5f040c4fddbc6927fbc0c56ab34a1e7a951 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -801,7 +801,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
                RTLIL::Module *mod;
                void operator()(RTLIL::SigSpec &sig)
                {
-                       for (auto &c : sig.chunks())
+                       for (auto &c : sig.chunks_rw())
                                if (c.wire != NULL)
                                        c.wire = mod->wires.at(c.wire->name);
                }

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 6bbf69602076c18d3d370d793a28328688838b56..9d5b3b30468a9bf673aa5fea3b6690c2179e4c0b 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -501,7 +501,7 @@ private:
        int width_;
 
 public:
-       std::vector<RTLIL::SigChunk> &chunks() { return chunks_; }
+       std::vector<RTLIL::SigChunk> &chunks_rw() { return chunks_; }
        const std::vector<RTLIL::SigChunk> &chunks() const { return chunks_; }
 
        int size() const { return width_; }

diff --git a/kernel/sigtools.h b/kernel/sigtools.h
index 27abd86700d9f8acfb58e314bf3a0495b8e81e02..826f84179ef69e38185868de443e3a4db94e209b 100644 (file)
--- a/kernel/sigtools.h
+++ b/kernel/sigtools.h
@@ -423,8 +423,8 @@ struct SigMap
                assert(from.chunks().size() == to.chunks().size());
                for (size_t i = 0; i < from.chunks().size(); i++)
                {
-                       RTLIL::SigChunk &cf = from.chunks()[i];
-                       RTLIL::SigChunk &ct = to.chunks()[i];
+                       const RTLIL::SigChunk &cf = from.chunks()[i];
+                       const RTLIL::SigChunk &ct = to.chunks()[i];
 
                        if (cf.wire == NULL)
                                continue;
@@ -444,7 +444,7 @@ struct SigMap
                sig.expand();
                for (size_t i = 0; i < sig.chunks().size(); i++)
                {
-                       RTLIL::SigChunk &c = sig.chunks()[i];
+                       const RTLIL::SigChunk &c = sig.chunks()[i];
                        if (c.wire != NULL) {
                                register_bit(c);
                                set_bit(c, c);
@@ -462,7 +462,7 @@ struct SigMap
        void apply(RTLIL::SigSpec &sig) const
        {
                sig.expand();
-               for (auto &c : sig.chunks())
+               for (auto &c : sig.chunks_rw())
                        map_bit(c);
                sig.optimize();
        }

diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc
index c5aa196c6fb6afcc411e13d4c490a76c624b99e2..f433c4b4adc520dd5e11932746beec925b15c6ae 100644 (file)
--- a/passes/cmds/delete.cc
+++ b/passes/cmds/delete.cc
@@ -28,7 +28,7 @@ struct DeleteWireWorker
 
        void operator()(RTLIL::SigSpec &sig) {
                sig.optimize();
-               for (auto &c : sig.chunks())
+               for (auto &c : sig.chunks_rw())
                        if (c.wire != NULL && delete_wires_p->count(c.wire->name)) {
                                c.wire = module->addWire(NEW_ID, c.width);
                                c.offset = 0;

diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 7558a4e9abd26297c316095c41719ee279a77514..619930b3a1c1b28f3477e0e1f82a51da7e199cee 100644 (file)
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -48,7 +48,7 @@ struct SetundefWorker
        void operator()(RTLIL::SigSpec &sig)
        {
                sig.expand();
-               for (auto &c : sig.chunks())
+               for (auto &c : sig.chunks_rw())
                        if (c.wire == NULL && c.data.bits.at(0) > RTLIL::State::S1)
                                c.data.bits.at(0) = next_bit();
                sig.optimize();

diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index fde96d5375bb6a90ca595d7fb08160e421eed53c..37fe440471f6b4f340d86975f5d0525d8a7427c0 100644 (file)
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -179,7 +179,7 @@ struct ShowWorker
                }
 
                if (sig.chunks().size() == 1) {
-                       RTLIL::SigChunk &c = sig.chunks()[0];
+                       const RTLIL::SigChunk &c = sig.chunks()[0];
                        if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) {
                                if (!range_check || c.wire->width == c.width)
                                                return stringf("n%d", id2num(c.wire->name));
@@ -203,7 +203,7 @@ struct ShowWorker
                        int pos = sig.size()-1;
                        int idx = single_idx_count++;
                        for (int i = int(sig.chunks().size())-1; i >= 0; i--) {
-                               RTLIL::SigChunk &c = sig.chunks()[i];
+                               const RTLIL::SigChunk &c = sig.chunks()[i];
                                net = gen_signode_simple(c, false);
                                assert(!net.empty());
                                if (driver) {

diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index 8cc6a5152e0ce2065a2a6af7782f8e77c9dc3364..d71e9727c312bf5df1de92876f2c12fd32721e28 100644 (file)
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -63,7 +63,7 @@ struct SplitnetsWorker
        void operator()(RTLIL::SigSpec &sig)
        {
                sig.expand();
-               for (auto &c : sig.chunks())
+               for (auto &c : sig.chunks_rw())
                        if (splitmap.count(c.wire) > 0)
                                c = splitmap.at(c.wire).at(c.offset);
                sig.optimize();

diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index 701b09bd893e791449b97618f1ad27c2e253cb99..c3bb1933a20b1477b632e4b79d6897cbcbbb6d65 100644 (file)
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -92,7 +92,7 @@ static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State no
 {
        if (dont_care.size() > 0) {
                sig.expand();
-               for (auto &chunk : sig.chunks()) {
+               for (auto &chunk : sig.chunks_rw()) {
                        assert(chunk.width == 1);
                        if (dont_care.extract(chunk).size() > 0)
                                chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state);
@@ -104,7 +104,7 @@ static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State no
        ce.values_map.apply(sig);
 
        sig.expand();
-       for (auto &chunk : sig.chunks()) {
+       for (auto &chunk : sig.chunks_rw()) {
                assert(chunk.width == 1);
                if (chunk.wire != NULL)
                        chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state);

diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index fa8043c899649c7128a2f6e5ff171f684fa6a7af..b983a840e6a3eefe31b3389802767c2704473ea8 100644 (file)
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -164,7 +164,7 @@ struct SubmodWorker
                for (RTLIL::Cell *cell : submod.cells) {
                        RTLIL::Cell *new_cell = new RTLIL::Cell(*cell);
                        for (auto &conn : new_cell->connections)
-                               for (auto &c : conn.second.chunks())
+                               for (auto &c : conn.second.chunks_rw())
                                        if (c.wire != NULL) {
                                                assert(wire_flags.count(c.wire) > 0);
                                                c.wire = wire_flags[c.wire].new_wire;

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 8bae24cff3b50e3e60c18776ea74937dda4a2e18..dee48597fbef6513b4d212b585425b4a44eb6ef3 100644 (file)
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -36,7 +36,7 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 
        for (size_t i = 0; i < sig.chunks().size(); i++)
        {
-               RTLIL::SigChunk &chunk = sig.chunks()[i];
+               RTLIL::SigChunk &chunk = sig.chunks_rw()[i];
 
                if (chunk.wire == NULL)
                        continue;

diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 1a1f0fe4205cd79efb0a1b59ba157d4357f4bdb8..9b89291b15474e53004ea97c75a4552a09720a55 100644 (file)
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -699,10 +699,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
                        RTLIL::SigSpec a = cell->connections["\\A"]; \
                        assign_map.apply(a); \
                        if (a.is_fully_const()) { \
-                               a.optimize(); \
-                               if (a.chunks().empty()) a.chunks().push_back(RTLIL::SigChunk()); \
                                RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
-                               RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks()[0].data, dummy_arg, \
+                               RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), dummy_arg, \
                                                cell->parameters["\\A_SIGNED"].as_bool(), false, \
                                                cell->parameters["\\Y_WIDTH"].as_int())); \
                                replace_cell(module, cell, stringf("%s", log_signal(a)), "\\Y", y); \
@@ -715,10 +713,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
                        RTLIL::SigSpec b = cell->connections["\\B"]; \
                        assign_map.apply(a), assign_map.apply(b); \
                        if (a.is_fully_const() && b.is_fully_const()) { \
-                               a.optimize(), b.optimize(); \
-                               if (a.chunks().empty()) a.chunks().push_back(RTLIL::SigChunk()); \
-                               if (b.chunks().empty()) b.chunks().push_back(RTLIL::SigChunk()); \
-                               RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks()[0].data, b.chunks()[0].data, \
+                               RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \
                                                cell->parameters["\\A_SIGNED"].as_bool(), \
                                                cell->parameters["\\B_SIGNED"].as_bool(), \
                                                cell->parameters["\\Y_WIDTH"].as_int())); \

diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index b5763508a0a381ea1abb6cedf393a1b9fef4f8c1..6cb560f5c67cfcd032e82fca5a4bcf3b2c59d6f3 100644 (file)
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -168,7 +168,7 @@ restart_proc_arst:
                                        rspec.expand(), rval.expand();
                                        for (int i = 0; i < int(rspec.chunks().size()); i++)
                                                if (rspec.chunks()[i].wire == NULL)
-                                                       rval.chunks()[i] = rspec.chunks()[i];
+                                                       rval.chunks_rw()[i] = rspec.chunks()[i];
                                        rspec.optimize(), rval.optimize();
                                        RTLIL::SigSpec last_rval;
                                        for (int count = 0; rval != last_rval; count++) {

diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index 03a86246c1634f33f27ac4f1898e46dc39da8a6a..73235e930d4bc4551a1c31080adc92afaf0be492 100644 (file)
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -73,7 +73,7 @@ struct BruteForceEquivChecker
                        sig1.expand(), sig2.expand();
                        for (size_t i = 0; i < sig1.chunks().size(); i++)
                                if (sig1.chunks().at(i) == RTLIL::SigChunk(RTLIL::State::Sx))
-                                       sig2.chunks().at(i) = RTLIL::SigChunk(RTLIL::State::Sx);
+                                       sig2.chunks_rw().at(i) = RTLIL::SigChunk(RTLIL::State::Sx);
                        sig1.optimize(), sig2.optimize();
                }
 
@@ -299,7 +299,7 @@ struct VlogHammerReporter
                                                log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name));
                                        for (int i = 0; i < sig.size(); i++)
                                                if (rtl_sig.chunks().at(i).data.bits.at(0) == RTLIL::State::Sx)
-                                                       sig.chunks().at(i).data.bits.at(0) = RTLIL::State::Sx;
+                                                       sig.chunks_rw().at(i).data.bits.at(0) = RTLIL::State::Sx;
                                }
 
                                log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str());

diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index a960f2bae050178ea837455e5b2c037015abe767..5a7298087755e4ca625a2d1eeee016943772faa8 100644 (file)
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -756,7 +756,7 @@ struct ExtractPass : public Pass {
                                        newCell->parameters = cell->parameters;
                                        for (auto &conn : cell->connections) {
                                                RTLIL::SigSpec sig = sigmap(conn.second);
-                                               for (auto &chunk : sig.chunks())
+                                               for (auto &chunk : sig.chunks_rw())
                                                        if (chunk.wire != NULL)
                                                                chunk.wire = newMod->wires.at(chunk.wire->name);
                                                newCell->connections[conn.first] = sig;

diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index ac41e47caf93f47ac044f2a01ac6bd75cd9db8be..53c5d1044e589dee052258a08277f292dd796eb0 100644 (file)
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -31,7 +31,7 @@ static RTLIL::SigChunk last_hi, last_lo;
 void hilomap_worker(RTLIL::SigSpec &sig)
 {
        sig.expand();
-       for (auto &c : sig.chunks()) {
+       for (auto &c : sig.chunks_rw()) {
                if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) {
                        if (!singleton_mode || last_hi.width == 0) {
                                last_hi = RTLIL::SigChunk(module->addWire(NEW_ID));

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index d3e7e20fc4c10b324bc62eddc76c832f68fc8557..f3b1a0ef7a8ce8b6ff63919480e6467449e2933c 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -47,7 +47,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module
                std::string wire_name = sig.chunks()[i].wire->name;
                apply_prefix(prefix, wire_name);
                assert(module->wires.count(wire_name) > 0);
-               sig.chunks()[i].wire = module->wires[wire_name];
+               sig.chunks_rw()[i].wire = module->wires[wire_name];
        }
 }