Fix formatting for msys2 mingw build using GetSize

diff --git a/Makefile b/Makefile
index c3386446995a4bed945c958e5992ec4f6fb3cd92..d049c2edab0dc7ad29391094ee2d663c493305a4 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -869,9 +869,11 @@ config-mxe: clean
 
 config-msys2: clean
        echo 'CONFIG := msys2' > Makefile.conf
+       echo 'ENABLE_PLUGINS := 0' >> Makefile.conf
 
 config-msys2-64: clean
        echo 'CONFIG := msys2-64' > Makefile.conf
+       echo 'ENABLE_PLUGINS := 0' >> Makefile.conf
 
 config-cygwin: clean
        echo 'CONFIG := cygwin' > Makefile.conf

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 69f63486c8605a39c0b971c7e5cf7f7d368487b4..9f56d1ab639bc95b99c90d7e5a51e500d9337930 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -610,15 +610,15 @@ struct XAigerWriter
                        std::stringstream h_buffer;
                        auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
                        write_h_buffer(1);
-                       log_debug("ciNum = %zu\n", input_bits.size() + ci_bits.size());
+                       log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ci_bits));
                        write_h_buffer(input_bits.size() + ci_bits.size());
-                       log_debug("coNum = %zu\n", output_bits.size() + co_bits.size());
+                       log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(co_bits));
                        write_h_buffer(output_bits.size() + co_bits.size());
-                       log_debug("piNum = %zu\n", input_bits.size());
+                       log_debug("piNum = %d\n", GetSize(input_bits));
                        write_h_buffer(input_bits.size());
-                       log_debug("poNum = %zu\n", output_bits.size());
+                       log_debug("poNum = %d\n", GetSize(output_bits));
                        write_h_buffer(output_bits.size());
-                       log_debug("boxNum = %zu\n", box_list.size());
+                       log_debug("boxNum = %d\n", GetSize(box_list));
                        write_h_buffer(box_list.size());
 
                        RTLIL::Module *holes_module = nullptr;
@@ -772,7 +772,7 @@ struct XAigerWriter
 
                                if (output_bits.count(b)) {
                                        int o = ordered_outputs.at(b);
-                                       output_lines[o] += stringf("output %lu %d %s\n", o - co_bits.size(), i, log_id(wire));
+                                       output_lines[o] += stringf("output %d %d %s\n", o - GetSize(co_bits), i, log_id(wire));
                                        continue;
                                }
 

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 03c541b7cf4bd85d61810b51cd468a0bd3355a3e..bb97c5703de3f4c6df82b8ea238e44d4a599a579 100644 (file)
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -301,7 +301,11 @@ static uint32_t parse_xaiger_literal(std::istream &f)
        uint32_t l;
        f.read(reinterpret_cast<char*>(&l), sizeof(l));
        if (f.gcount() != sizeof(l))
+#if defined(_WIN32) && defined(__MINGW32__)
+               log_error("Offset %I64d: unable to read literal!\n", static_cast<int64_t>(f.tellg()));
+#else
                log_error("Offset %" PRId64 ": unable to read literal!\n", static_cast<int64_t>(f.tellg()));
+#endif
        return from_big_endian(l);
 }
 

diff --git a/misc/launcher.c b/misc/launcher.c
index 157d68cf306921262729981d9442fd23b8c4d3c0..e0d8208f1da8e65bb35931e36b9a3cd1f64a6ac9 100644 (file)
--- a/misc/launcher.c
+++ b/misc/launcher.c
@@ -61,6 +61,7 @@ SOFTWARE. */
 #include <windows.h>
 #include <tchar.h>
 #include <fcntl.h>
+#include <unistd.h>
 
 int child_pid=0;
 
@@ -338,7 +339,7 @@ int run(int argc, char **argv, int is_gui) {
 
     if (is_gui) {
         /* Use exec, we don't need to wait for the GUI to finish */
-        execv(ptr, (const char * const *)(newargs));
+        execv(ptr, (char * const *)(newargs));
         return fail("Could not exec %s", ptr);   /* shouldn't get here! */
     }
 

diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index 182f63d996dba07322a34caf1a424bf02340bc25..587ef878a6d68728fa2a93ccc7bc7fb7cb54be5e 100644 (file)
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -81,7 +81,7 @@ struct OptLutWorker
                        }
                }
 
-               log("Number of LUTs: %8zu\n", luts.size());
+               log("Number of LUTs: %8d\n", GetSize(luts));
                for (int arity = 1; arity <= max_arity; arity++)
                {
                        if (arity_counts[arity])
@@ -351,14 +351,14 @@ struct OptLutWorker
 
                                        int lutM_arity = lutA_arity + lutB_arity - 1 - common_inputs.size();
                                        if (lutA_dlogic_inputs.size())
-                                               log_debug("  Cell A is a %d-LUT with %zu dedicated connections. ", lutA_arity, lutA_dlogic_inputs.size());
+                                               log_debug("  Cell A is a %d-LUT with %d dedicated connections. ", lutA_arity, GetSize(lutA_dlogic_inputs));
                                        else
                                                log_debug("  Cell A is a %d-LUT. ", lutA_arity);
                                        if (lutB_dlogic_inputs.size())
-                                               log_debug("Cell B is a %d-LUT with %zu dedicated connections.\n", lutB_arity, lutB_dlogic_inputs.size());
+                                               log_debug("Cell B is a %d-LUT with %d dedicated connections.\n", lutB_arity, GetSize(lutB_dlogic_inputs));
                                        else
                                                log_debug("Cell B is a %d-LUT.\n", lutB_arity);
-                                       log_debug("  Cells share %zu input(s) and can be merged into one %d-LUT.\n", common_inputs.size(), lutM_arity);
+                                       log_debug("  Cells share %d input(s) and can be merged into one %d-LUT.\n", GetSize(common_inputs), lutM_arity);
 
                                        const int COMBINE_A = 1, COMBINE_B = 2, COMBINE_EITHER = COMBINE_A | COMBINE_B;
                                        int combine_mask = 0;

diff --git a/passes/opt/rmports.cc b/passes/opt/rmports.cc
index fc1596ebf4e95b17385764c730c32f72c3b92828..32363dd681efab4939345f3399db03a7583083b5 100644 (file)
--- a/passes/opt/rmports.cc
+++ b/passes/opt/rmports.cc
@@ -171,7 +171,7 @@ struct RmportsPassPass : public Pass {
                        wire->port_output = false;
                        wire->port_id = 0;
                }
-               log("Removed %zu unused ports.\n", unused_ports.size());
+               log("Removed %d unused ports.\n", GetSize(unused_ports));
 
                // Re-number all of the wires that DO have ports still on them
                for(size_t i=0; i<module->ports.size(); i++)

diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
index f5892a60ecb3d450103c1858d007e163d89d0f60..96d0df5f8b3c3632e7a1d1134d2ce804708fd998 100644 (file)
--- a/passes/techmap/flowmap.cc
+++ b/passes/techmap/flowmap.cc
@@ -783,7 +783,7 @@ struct FlowmapWorker
                int depth = 0;
                for (auto label : labels)
                        depth = max(depth, label.second);
-               log("Mapped to %zu LUTs with maximum depth %d.\n", lut_nodes.size(), depth);
+               log("Mapped to %d LUTs with maximum depth %d.\n", GetSize(lut_nodes), depth);
 
                if (debug)
                {
@@ -1195,7 +1195,7 @@ struct FlowmapWorker
 
        bool relax_depth_for_bound(bool first, int depth_bound, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> &lut_critical_outputs)
        {
-               size_t initial_count = lut_nodes.size();
+               int initial_count = GetSize(lut_nodes);
 
                for (auto node : lut_nodes)
                {
@@ -1215,7 +1215,7 @@ struct FlowmapWorker
 
                        if (potentials.empty())
                        {
-                               log("  Relaxed to %zu (+%zu) LUTs.\n", lut_nodes.size(), lut_nodes.size() - initial_count);
+                               log("  Relaxed to %d (+%d) LUTs.\n", GetSize(lut_nodes), GetSize(lut_nodes) - initial_count);
                                if (!first && break_num == 1)
                                {
                                        log("  Design fully relaxed.\n");
@@ -1419,9 +1419,9 @@ struct FlowmapWorker
                        lut_area += lut_table.size();
 
                        if ((int)input_nodes.size() >= minlut)
-                               log("  Packed into a %zu-LUT %s.%s.\n", input_nodes.size(), log_id(module), log_id(lut));
+                               log("  Packed into a %d-LUT %s.%s.\n", GetSize(input_nodes), log_id(module), log_id(lut));
                        else
-                               log("  Packed into a %zu-LUT %s.%s (implemented as %d-LUT).\n", input_nodes.size(), log_id(module), log_id(lut), minlut);
+                               log("  Packed into a %d-LUT %s.%s (implemented as %d-LUT).\n", GetSize(input_nodes), log_id(module), log_id(lut), minlut);
                }
 
                for (auto node : mapped_nodes)

diff --git a/techlibs/anlogic/anlogic_determine_init.cc b/techlibs/anlogic/anlogic_determine_init.cc
index 34b1d4f8a4323b8500bc316906c02e403801d52f..c4089dac20d776c42c4170bb6011f8512f694818 100644 (file)
--- a/techlibs/anlogic/anlogic_determine_init.cc
+++ b/techlibs/anlogic/anlogic_determine_init.cc
@@ -50,7 +50,7 @@ struct AnlogicDetermineInitPass : public Pass {
 
                extra_args(args, args.size(), design);
 
-               size_t cnt = 0;
+               int cnt = 0;
                for (auto module : design->selected_modules())
                {
                        for (auto cell : module->selected_cells())
@@ -65,7 +65,7 @@ struct AnlogicDetermineInitPass : public Pass {
                                }
                        }
                }
-               log_header(design, "Updated %lu cells with determined init value.\n", cnt);
+               log_header(design, "Updated %d cells with determined init value.\n", cnt);
        }
 } AnlogicDetermineInitPass;
 

diff --git a/techlibs/anlogic/anlogic_eqn.cc b/techlibs/anlogic/anlogic_eqn.cc
index 741bf04cc494025fcb6e53c7492b951094cd9055..070d39a20c39cd930732c6ac155e1ffffb382a82 100644 (file)
--- a/techlibs/anlogic/anlogic_eqn.cc
+++ b/techlibs/anlogic/anlogic_eqn.cc
@@ -69,7 +69,7 @@ struct AnlogicEqnPass : public Pass {
 
                extra_args(args, args.size(), design);
 
-               size_t cnt = 0;
+               int cnt = 0;
                for (auto module : design->selected_modules())
                {
                        for (auto cell : module->selected_cells())
@@ -106,7 +106,7 @@ struct AnlogicEqnPass : public Pass {
                                }
                        }
                }
-               log_header(design, "Updated %lu of AL_MAP_LUT* elements with equation.\n", cnt);
+               log_header(design, "Updated %d of AL_MAP_LUT* elements with equation.\n", cnt);
        }
 } AnlogicEqnPass;
 

diff --git a/techlibs/gowin/determine_init.cc b/techlibs/gowin/determine_init.cc
index 991e5245a8699c2a6a045580382cec2278e876fd..d9a0880f6ccd53ee340d89703b43b9941698971e 100644 (file)
--- a/techlibs/gowin/determine_init.cc
+++ b/techlibs/gowin/determine_init.cc
@@ -50,7 +50,7 @@ struct DetermineInitPass : public Pass {
 
                extra_args(args, args.size(), design);
 
-               size_t cnt = 0;
+               int cnt = 0;
                for (auto module : design->selected_modules())
                {
                        for (auto cell : module->selected_cells())
@@ -65,7 +65,7 @@ struct DetermineInitPass : public Pass {
                                }
                        }
                }
-               log_header(design, "Updated %lu cells with determined init value.\n", cnt);
+               log_header(design, "Updated %d cells with determined init value.\n", cnt);
        }
 } DetermineInitPass;