power_insn: support dz/sz specifiers

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index b35d504f757aa5e808a6d89329185784c78f4626..eb04abad09e9ac8f16fe7146b64ac0a57ec424ba 100644 (file)
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1305,6 +1305,14 @@ class NormalRM(BaseRM):
         dz: BaseRM.mode[3]
         sz: BaseRM.mode[4]
 
+        @property
+        def specifiers(self):
+            if self.dz:
+                yield f"dz"
+            if self.sz:
+                yield f"sz"
+            yield from super().specifiers
+
     class smr(BaseRM):
         """normal: scalar reduce mode (mapreduce), SUBVL=1"""
         RG: BaseRM.mode[4]
@@ -1334,6 +1342,14 @@ class NormalRM(BaseRM):
         dz: BaseRM.mode[3]
         sz: BaseRM.mode[4]
 
+        @property
+        def specifiers(self):
+            if self.dz:
+                yield f"dz"
+            if self.sz:
+                yield f"sz"
+            yield from super().specifiers
+
     class satx(BaseRM):
         """normal: sat mode: N=0/1 u/s, SUBVL>1"""
         N: BaseRM.mode[2]
@@ -1341,6 +1357,29 @@ class NormalRM(BaseRM):
         dz: BaseRM.mode[3]
         sz: BaseRM.mode[3]
 
+        @property
+        def specifiers(self):
+            if self.dz:
+                yield f"dz"
+            if self.sz:
+                yield f"sz"
+            yield from super().specifiers
+
+    class satpu(BaseRM):
+        """normal: Pack/Unpack sat mode: N=0/1 u/s, SUBVL>1"""
+        N: BaseRM.mode[2]
+        zz: BaseRM.mode[3]
+        dz: BaseRM.mode[3]
+        sz: BaseRM.mode[3]
+
+        @property
+        def specifiers(self):
+            if self.dz:
+                yield f"dz"
+            if self.sz:
+                yield f"sz"
+            yield from super().specifiers
+
     class prrc1(BaseRM):
         """normal: Rc=1: pred-result CR sel"""
         inv: BaseRM.mode[2]
@@ -1354,6 +1393,14 @@ class NormalRM(BaseRM):
         dz: BaseRM.mode[3]
         sz: BaseRM.mode[3]
 
+        @property
+        def specifiers(self):
+            if self.dz:
+                yield f"dz"
+            if self.sz:
+                yield f"sz"
+            yield from super().specifiers
+
     simple: simple
     smr: smr
     pmr: pmr
@@ -1374,6 +1421,29 @@ class LDSTImmRM(BaseRM):
         dz: BaseRM.mode[3]
         sz: BaseRM.mode[3]
 
+        @property
+        def specifiers(self):
+            if self.dz:
+                yield f"dz"
+            if self.sz:
+                yield f"sz"
+            yield from super().specifiers
+
+    class spu(BaseRM):
+        """ld/st immediate: Structured Pack/Unpack"""
+        zz: BaseRM.mode[3]
+        els: BaseRM.mode[4]
+        dz: BaseRM.mode[3]
+        sz: BaseRM.mode[3]
+
+        @property
+        def specifiers(self):
+            if self.dz:
+                yield f"dz"
+            if self.sz:
+                yield f"sz"
+            yield from super().specifiers
+
     class ffrc1(BaseRM):
         """ld/st immediate: Rc=1: ffirst CR sel"""
         inv: BaseRM.mode[2]
@@ -1393,6 +1463,14 @@ class LDSTImmRM(BaseRM):
         dz: BaseRM.mode[3]
         sz: BaseRM.mode[3]
 
+        @property
+        def specifiers(self):
+            if self.dz:
+                yield f"dz"
+            if self.sz:
+                yield f"sz"
+            yield from super().specifiers
+
     class prrc1(BaseRM):
         """ld/st immediate: Rc=1: pred-result CR sel"""
         inv: BaseRM.mode[2]
@@ -1419,18 +1497,42 @@ class LDSTIdxRM(BaseRM):
         sz: BaseRM.mode[3]
         dz: BaseRM.mode[3]
 
+        @property
+        def specifiers(self):
+            if self.dz:
+                yield f"dz"
+            if self.sz:
+                yield f"sz"
+            yield from super().specifiers
+
     class stride(BaseRM):
         """ld/st index: strided (scalar only source)"""
         SEA: BaseRM.mode[2]
         dz: BaseRM.mode[3]
         sz: BaseRM.mode[4]
 
+        @property
+        def specifiers(self):
+            if self.dz:
+                yield f"dz"
+            if self.sz:
+                yield f"sz"
+            yield from super().specifiers
+
     class sat(BaseRM):
         """ld/st index: sat mode: N=0/1 u/s"""
         N: BaseRM.mode[2]
         dz: BaseRM.mode[3]
         sz: BaseRM.mode[4]
 
+        @property
+        def specifiers(self):
+            if self.dz:
+                yield f"dz"
+            if self.sz:
+                yield f"sz"
+            yield from super().specifiers
+
     class prrc1(BaseRM):
         """ld/st index: Rc=1: pred-result CR sel"""
         inv: BaseRM.mode[2]
@@ -1444,6 +1546,14 @@ class LDSTIdxRM(BaseRM):
         dz: BaseRM.mode[3]
         sz: BaseRM.mode[3]
 
+        @property
+        def specifiers(self):
+            if self.dz:
+                yield f"dz"
+            if self.sz:
+                yield f"sz"
+            yield from super().specifiers
+
     simple: simple
     stride: stride
     sat: sat
@@ -1459,12 +1569,26 @@ class CROpRM(BaseRM):
         RG: BaseRM[20]
         dz: BaseRM[22]
 
+        @property
+        def specifiers(self):
+            if self.dz:
+                yield f"dz"
+            if self.sz:
+                yield f"sz"
+            yield from super().specifiers
+
     class smr(BaseRM):
         """cr_op: scalar reduce mode (mapreduce), SUBVL=1"""
         sz: BaseRM[6]
         SNZ: BaseRM[7]
         RG: BaseRM[20]
 
+        @property
+        def specifiers(self):
+            if self.sz:
+                yield f"sz"
+            yield from super().specifiers
+
     class svmr(BaseRM):
         """cr_op: subvector reduce mode, SUBVL>1"""
         zz: BaseRM[6]
@@ -1474,6 +1598,14 @@ class CROpRM(BaseRM):
         dz: BaseRM[6]
         sz: BaseRM[6]
 
+        @property
+        def specifiers(self):
+            if self.dz:
+                yield f"dz"
+            if self.sz:
+                yield f"sz"
+            yield from super().specifiers
+
     class reserved(BaseRM):
         """cr_op: reserved"""
         zz: BaseRM[6]
@@ -1482,6 +1614,14 @@ class CROpRM(BaseRM):
         dz: BaseRM[6]
         sz: BaseRM[6]
 
+        @property
+        def specifiers(self):
+            if self.dz:
+                yield f"dz"
+            if self.sz:
+                yield f"sz"
+            yield from super().specifiers
+
     class ff3(BaseRM):
         """cr_op: ffirst 3-bit mode"""
         zz: BaseRM[6]
@@ -1492,15 +1632,29 @@ class CROpRM(BaseRM):
         dz: BaseRM[6]
         sz: BaseRM[6]
 
+        @property
+        def specifiers(self):
+            if self.dz:
+                yield f"dz"
+            if self.sz:
+                yield f"sz"
+            yield from super().specifiers
+
     class ff5(BaseRM):
         """cr_op: ffirst 5-bit mode"""
-        zz: BaseRM[6]
+        sz: BaseRM[6]
         SNZ: BaseRM[7]
         VLI: BaseRM[20]
         inv: BaseRM[21]
         dz: BaseRM[22]
-        dz: BaseRM[6]
-        sz: BaseRM[6]
+
+        @property
+        def specifiers(self):
+            if self.dz:
+                yield f"dz"
+            if self.sz:
+                yield f"sz"
+            yield from super().specifiers
 
     simple: simple
     smr: smr