virtual ~OutputWriter() {};
virtual void write_header() = 0;
virtual void write_step_header(int t) = 0;
- virtual void enter_scope(IdString name) = 0;
- virtual void exit_scope() = 0;
- virtual void register_signal(Wire *wire, int id) = 0;
- virtual void write_value(int id, Const& value) = 0;
+ virtual void enter_scope(IdString) {};
+ virtual void exit_scope() {};
+ virtual void register_signal(Wire *, int) {};
+ virtual void write_value(int, Const&) {};
SimWorker *worker;
};
{
vcdfile << stringf("$scope module %s $end\n", log_id(name));
}
+
void exit_scope() override
{
vcdfile << stringf("$upscope $end\n");
default: vcdfile << "z";
}
}
-
vcdfile << stringf(" n%d\n", id);
}
mapping.emplace(id, fst_id);
}
+
void write_value(int id, Const& value) override
{
if (!fstfile) return;
}
fstWriterEmitValueChange(fstfile, mapping[id], ss.str().c_str());
}
+
struct fstContext *fstfile = nullptr;
std::map<int,fstHandle> mapping;
};
break;
}
}
-
- void enter_scope(IdString) override {}
- void exit_scope() override {}
- void register_signal(Wire*, int) override {}
- void write_value(int , Const& ) override {}
std::ofstream aiwfile;
dict<int, std::pair<SigBit, bool>> aiw_latches;