// Since we don't simulate a FIFO for incoming data, we
// assume it's empty and clear RXINTR and RTINTR.
clearInterrupts(UART_RXINTR | UART_RTINTR);
+ if (term->dataAvailable()) {
+ DPRINTF(Uart, "Re-raising interrupt due to more data "
+ "after UART_DR read\n");
+ dataAvailable();
+ }
}
break;
case UART_FR:
case UART_ICR:
DPRINTF(Uart, "Clearing interrupts 0x%x\n", data);
clearInterrupts(data);
+ if (term->dataAvailable()) {
+ DPRINTF(Uart, "Re-raising interrupt due to more data after "
+ "UART_ICR write\n");
+ dataAvailable();
+ }
break;
default:
panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr);