A few minor enhancements to specify block parsing.

Just remember specify blocks are parsed but ignored.

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 78cac5543936b0f7dc682e700e9905c203df4f9e..61da12b76b9e2c40e402862f3b7653c81b0613af 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -688,8 +688,8 @@ path_declaration :
        ;
 
 simple_path_declaration :
-       parallel_path_description '=' path_delay_value ';'
-       // | full_path_description '=' path_delay_value ';'
+       parallel_path_description '=' path_delay_value ';' |
+       full_path_description '=' path_delay_value ';'
        ;
 
 path_delay_value :
@@ -723,6 +723,17 @@ list_of_path_delay_expressions :
 parallel_path_description :
        '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ;
 
+full_path_description :
+       '(' list_of_path_inputs opt_polarity_operator '*' '>' list_of_path_outputs ')' ;
+
+list_of_path_inputs :
+       specify_input_terminal_descriptor |
+       list_of_path_inputs ',' specify_input_terminal_descriptor ;
+       
+list_of_path_outputs :
+       specify_output_terminal_descriptor |
+       list_of_path_outputs ',' specify_output_terminal_descriptor ;
+       
 opt_polarity_operator :
        '+'
        | '-'