soc: rename with_sdram option to with_main_ram (with_sdram was confusing)

diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py
index 03f852beb46ad4188089f4ed7eac6ce5d68d05ed..b22d4cfa938df6edd20b18ae80ae4451d9bb70e2 100644 (file)
--- a/misoclib/soc/__init__.py
+++ b/misoclib/soc/__init__.py
@@ -39,7 +39,7 @@ class SoC(Module):
                                                           cpu_boot_file="software/bios/bios.bin",
                                with_rom=False, rom_size=0x8000,
                                with_sram=True, sram_size=4096,
-                               with_sdram=False, sdram_size=64*1024,
+                               with_main_ram=False, main_ram_size=64*1024,
                                with_csr=True, csr_data_width=8, csr_address_width=14,
                                with_uart=True, uart_baudrate=115200,
                                with_identifier=True,
@@ -62,8 +62,8 @@ class SoC(Module):
                self.with_sram = with_sram
                self.sram_size = sram_size
 
-               self.with_sdram = with_sdram
-               self.sdram_size = sdram_size
+               self.with_main_ram = with_main_ram
+               self.main_ram_size = main_ram_size
 
                self.with_uart = with_uart
                self.uart_baudrate = uart_baudrate
@@ -98,9 +98,10 @@ class SoC(Module):
                                self.submodules.sram = wishbone.SRAM(sram_size)
                                self.register_mem("sram", self.mem_map["sram"], self.sram.bus, sram_size)
 
-                       if with_sdram:
-                               self.submodules.sdram = wishbone.SRAM(sdram_size)
-                               self.register_mem("sdram", self.mem_map["sdram"], self.sdram.bus, sdram_size)
+                       # Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
+                       if with_main_ram:
+                               self.submodules.main_ram = wishbone.SRAM(main_ram_size)
+                               self.register_mem("sdram", self.mem_map["sdram"], self.main_ram.bus, main_ram_size)
 
                elif cpu_or_bridge is not None and not isinstance(cpu_or_bridge, CPU):
                        self._wb_masters += [cpu_or_bridge.wishbone]

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index e6ecb9304c2e15b7380f8ec9c00a7ac152e58a8d..7e47cf1d5018fe2e949e87fb384510f734f1533f 100644 (file)
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -60,25 +60,25 @@ class SDRAMSoC(SoC):
                                else:
                                        self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master())
                                lasmic = self.sdram.controller.lasmic
-                               sdram_size = 2**lasmic.aw*lasmic.dw*lasmic.nbanks//8
-                               self.register_mem("sdram", self.mem_map["sdram"], self.wishbone2lasmi.wishbone, sdram_size)
+                               main_ram_size = 2**lasmic.aw*lasmic.dw*lasmic.nbanks//8
+                               self.register_mem("sdram", self.mem_map["sdram"], self.wishbone2lasmi.wishbone, main_ram_size)
 
                # MINICON frontend
                elif self.ramcon_type == "minicon":
                        sdram_width = flen(self.sdram.controller.bus.dat_r)
-                       sdram_size = 2**(sdram_geom.bank_a+sdram_geom.row_a+sdram_geom.col_a)*sdram_width//8
+                       main_ram_size = 2**(sdram_geom.bank_a+sdram_geom.row_a+sdram_geom.col_a)*sdram_width//8
 
                        if sdram_width == 32:
-                               self.register_mem("sdram", self.mem_map["sdram"], self.sdram.controller.bus, sdram_size)
+                               self.register_mem("sdram", self.mem_map["sdram"], self.sdram.controller.bus, main_ram_size)
                        elif sdram_width < 32:
                                self.submodules.downconverter = downconverter = wishbone.DownConverter(32, sdram_width)
                                self.comb += Record.connect(downconverter.wishbone_o, self.sdram.controller.bus)
-                               self.register_mem("sdram", self.mem_map["sdram"], downconverter.wishbone_i, sdram_size)
+                               self.register_mem("sdram", self.mem_map["sdram"], downconverter.wishbone_i, main_ram_size)
                        else:
                                raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
 
        def do_finalize(self):
-               if not self.with_sdram:
+               if not self.with_main_ram:
                        if not self._sdram_phy_registered:
                                raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
                SoC.do_finalize(self)

diff --git a/targets/de0nano.py b/targets/de0nano.py
index 82ae5bd9d1a926e1b36a390bd6bdff48ec8bf9a5..769613ea07c73e359f1fa4f90da7b86840936262 100644 (file)
--- a/targets/de0nano.py
+++ b/targets/de0nano.py
@@ -89,7 +89,7 @@ class BaseSoC(SDRAMSoC):
 
                self.submodules.crg = _CRG(platform)
 
-               if not self.with_sdram:
+               if not self.with_main_ram:
                        sdram_geom = sdram.GeomSettings(
                                bank_a=2,
                                row_a=13,

diff --git a/targets/kc705.py b/targets/kc705.py
index 6eae2d1ded9038dd39b97bc4b272d85979019674..4390c1f0d98c8284464611c203266195ea61e9a9 100644 (file)
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -80,7 +80,7 @@ class BaseSoC(SDRAMSoC):
 
                self.submodules.crg = _CRG(platform)
 
-               if not self.with_sdram:
+               if not self.with_main_ram:
                        sdram_geom = sdram.GeomSettings(
                                bank_a=3,
                                row_a=16,

diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index b20d801f5307a4faec479a7c666da49a5155e119..0278b342e9dccbfc02757c9b2c2479045a68b12d 100644 (file)
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -40,7 +40,7 @@ class BaseSoC(SDRAMSoC):
 
                self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
 
-               if not self.with_sdram:
+               if not self.with_main_ram:
                        sdram_geom = sdram.GeomSettings(
                                bank_a=2,
                                row_a=13,

diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index 41c1447b9dc7d4eca52fc42cb261a743d12b5ff7..c2c58a06bd4c6e07f47ff2b16ab7a00e506ef73f 100644 (file)
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
@@ -96,7 +96,7 @@ class BaseSoC(SDRAMSoC):
 
                self.submodules.crg = _CRG(platform, clk_freq)
 
-               if not self.with_sdram:
+               if not self.with_main_ram:
                        sdram_geom = sdram.GeomSettings(
                                bank_a=2,
                                row_a=13,

diff --git a/targets/ppro.py b/targets/ppro.py
index 347f665ae0003e5dc3bad7e69110fe25f9cc3d65..c50e9bb48b8434aa4c3df2b0e274ddfa00b2bfd3 100644 (file)
--- a/targets/ppro.py
+++ b/targets/ppro.py
@@ -73,7 +73,7 @@ class BaseSoC(SDRAMSoC):
 
                self.submodules.crg = _CRG(platform, clk_freq)
 
-               if not self.with_sdram:
+               if not self.with_main_ram:
                        sdram_geom = sdram.GeomSettings(
                                bank_a=2,
                                row_a=12,

diff --git a/targets/simple.py b/targets/simple.py
index e828296c6f6fcf28f52db0b96d72c3c03055905c..eb8e183f14864d2fd62131465dc1c15e311d0365 100644 (file)
--- a/targets/simple.py
+++ b/targets/simple.py
@@ -10,7 +10,7 @@ class BaseSoC(SoC):
                SoC.__init__(self, platform,
                        clk_freq=int((1/(platform.default_clk_period))*1000000000),
                        with_rom=True,
-                       with_sdram=True, sdram_size=16*1024,
+                       with_main_ram=True, main_ram_size=16*1024,
                        **kwargs)
 
 class MiniSoC(BaseSoC):