"
{
operands[3] = gen_reg_rtx (SImode);
- if (CONSTANT_P (operands[2]))
+ if (GET_CODE (operands[2]) == CONST_INT
+ || GET_CODE (operands[2]) == CONST_DOUBLE)
{
- /* We have to rearrange the operand order for the matching constraints. */
+ if (! const_uint32_operand (operands[2]))
+ abort ();
+ /* We have to adjust the operand order for the matching constraints. */
emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
operands[1], operands[2]));
DONE;
(truncate:SI
(lshiftrt:DI
(mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
- (match_operand:DI 3 "immediate_operand" "i"))
+ (match_operand 3 "const_uint32_operand" ""))
(const_int 32))))
(clobber (match_operand:SI 1 "register_operand" "=d"))]
"TARGET_68020"
"
{
operands[3] = gen_reg_rtx (SImode);
- if (CONSTANT_P (operands[2]))
+ if (GET_CODE (operands[2]) == CONST_INT
+ || GET_CODE (operands[2]) == CONST_DOUBLE)
{
- /* We have to rearrange the operand order for the matching constraints. */
+ if (! const_sint32_operand (operands[2]))
+ abort ();
+ /* We have to adjust the operand order for the matching constraints. */
emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
operands[1], operands[2]));
DONE;
(truncate:SI
(lshiftrt:DI
(mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
- (match_operand:DI 3 "immediate_operand" "i"))
+ (match_operand 3 "const_sint32_operand" ""))
(const_int 32))))
(clobber (match_operand:SI 1 "register_operand" "=d"))]
"TARGET_68020"