* doc/c-mips.texi (MIPS Opts): Fix typo in last patch.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index feb81f8b79c736cf0af72d4d669bcea9ae264086..1bb6e382acff93c05832f19516b81b99703f4751 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2000-02-26  Andreas Jaeger  <aj@suse.de>
+
+       * doc/c-mips.texi (MIPS Opts): Fix typo in last patch.
+
 2000-02-25  Alan Modra  <alan@spri.levels.unisa.edu.au>
 
        * config/tc-i386.c (md_assemble): Don't swap intersegment jmp and

diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 6234b0c0b7d9b33a14649e28013a973abdae480c..26940deabc5ff557cea2c22bc0af52ba2055c805 100644 (file)
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -71,7 +71,7 @@ assembly; see @ref{MIPS ISA,, Directives to override the ISA level}.
 Assume that 32-bit general purpose registers are available.  This
 affects synthetic instructions such as @code{move}, which will assemble
 to a 32-bit or a 64-bit instruction depending on this flag.  On some
-MIPS variants there is be a 32-bit mode flag; when this flag is set,
+MIPS variants there is a 32-bit mode flag; when this flag is set,
 64-bit instructions generate a trap.  Also, some 32-bit OSes only save
 the 32-bit registers on a context switch, so it is essential never to
 use the 64-bit registers.