fs_visitor::IF(const fs_reg &src0, const fs_reg &src1,
enum brw_conditional_mod condition)
{
- assert(brw->gen == 6);
+ assert(devinfo->gen == 6);
fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF, dispatch_width,
reg_null_d, src0, src1);
inst->conditional_mod = condition;
varying_offset, fs_reg(const_offset & ~3)));
int scale = 1;
- if (brw->gen == 4 && dst.width == 8) {
+ if (devinfo->gen == 4 && dst.width == 8) {
/* Pre-gen5, we can either use a SIMD8 message that requires (header,
* u, v, r) as parameters, or we can just use the SIMD16 message
* consisting of (header, u). We choose the second, at the cost of a
}
enum opcode op;
- if (brw->gen >= 7)
+ if (devinfo->gen >= 7)
op = FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7;
else
op = FS_OPCODE_VARYING_PULL_CONSTANT_LOAD;
inst->regs_written = regs_written;
instructions.push_tail(inst);
- if (brw->gen < 7) {
+ if (devinfo->gen < 7) {
inst->base_mrf = 13;
inst->header_present = true;
- if (brw->gen == 4)
+ if (devinfo->gen == 4)
inst->mlen = 3;
else
inst->mlen = 1 + dispatch_width / 8;
}
bool
-fs_inst::can_do_source_mods(struct brw_context *brw)
+fs_inst::can_do_source_mods(const struct brw_device_info *devinfo)
{
- if (brw->gen == 6 && is_math())
+ if (devinfo->gen == 6 && is_math())
return false;
if (is_send_from_grf())
fs_reg
fs_visitor::get_timestamp(fs_inst **out_mov)
{
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
fs_reg ts = fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE,
BRW_ARF_TIMESTAMP,
wpos = offset(wpos, 1);
/* gl_FragCoord.z */
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
emit(MOV(wpos, fs_reg(brw_vec8_grf(payload.source_depth_reg, 0))));
} else {
emit(FS_OPCODE_LINTERP, wpos,
bool is_centroid, bool is_sample)
{
brw_wm_barycentric_interp_mode barycoord_mode;
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
if (is_centroid) {
if (interpolation_mode == INTERP_QUALIFIER_SMOOTH)
barycoord_mode = BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC;
/* Smooth/noperspective interpolation case. */
for (unsigned int k = 0; k < type->vector_elements; k++) {
struct brw_reg interp = interp_reg(location, k);
- if (brw->needs_unlit_centroid_workaround && mod_centroid) {
+ if (devinfo->needs_unlit_centroid_workaround && mod_centroid) {
/* Get the pixel/sample mask into f0 so that we know
* which pixels are lit. Then, for each channel that is
* unlit, replace the centroid data with non-centroid
false, false);
inst->predicate = BRW_PREDICATE_NORMAL;
inst->predicate_inverse = true;
- if (brw->has_pln)
+ if (devinfo->has_pln)
inst->no_dd_clear = true;
inst = emit_linterp(attr, fs_reg(interp), interpolation_mode,
mod_sample || key->persample_shading);
inst->predicate = BRW_PREDICATE_NORMAL;
inst->predicate_inverse = false;
- if (brw->has_pln)
+ if (devinfo->has_pln)
inst->no_dd_check = true;
} else {
mod_centroid && !key->persample_shading,
mod_sample || key->persample_shading);
}
- if (brw->gen < 6 && interpolation_mode == INTERP_QUALIFIER_SMOOTH) {
+ if (devinfo->gen < 6 && interpolation_mode == INTERP_QUALIFIER_SMOOTH) {
emit(BRW_OPCODE_MUL, attr, attr, this->pixel_w);
}
attr = offset(attr, 1);
{
fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::bool_type));
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
/* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
* a boolean result from this (~0/true or 0/false).
*
fs_reg *
fs_visitor::emit_samplepos_setup()
{
- assert(brw->gen >= 6);
+ assert(devinfo->gen >= 6);
this->current_annotation = "compute sample position";
fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::vec2_type));
{
assert(stage == MESA_SHADER_FRAGMENT);
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
- assert(brw->gen >= 6);
+ assert(devinfo->gen >= 6);
this->current_annotation = "compute sample id";
fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::int_type));
* The hardware ignores source modifiers (negate and abs) on math
* instructions, so we also move to a temp to set those up.
*/
- if (brw->gen == 6 && src.file != UNIFORM && src.file != IMM &&
+ if (devinfo->gen == 6 && src.file != UNIFORM && src.file != IMM &&
!src.abs && !src.negate)
return src;
/* Gen7 relaxes most of the above restrictions, but still can't use IMM
* operands to math
*/
- if (brw->gen >= 7 && src.file != IMM)
+ if (devinfo->gen >= 7 && src.file != IMM)
return src;
fs_reg expanded = vgrf(glsl_type::float_type);
* Gen 6 hardware ignores source modifiers (negate and abs) on math
* instructions, so we also move to a temp to set those up.
*/
- if (brw->gen == 6 || brw->gen == 7)
+ if (devinfo->gen == 6 || devinfo->gen == 7)
src = fix_math_operand(src);
fs_inst *inst = emit(opcode, dst, src);
- if (brw->gen < 6) {
+ if (devinfo->gen < 6) {
inst->base_mrf = 2;
inst->mlen = dispatch_width / 8;
}
int base_mrf = 2;
fs_inst *inst;
- if (brw->gen >= 8) {
+ if (devinfo->gen >= 8) {
inst = emit(opcode, dst, src0, src1);
- } else if (brw->gen >= 6) {
+ } else if (devinfo->gen >= 6) {
src0 = fix_math_operand(src0);
src1 = fix_math_operand(src1);
int urb_next = 0;
/* Figure out where each of the incoming setup attributes lands. */
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
if (_mesa_bitcount_64(prog->InputsRead &
BRW_FS_VARYING_INPUT_MASK) <= 16) {
/* The SF/SBE pipeline stage can do arbitrary rearrangement of the
{
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
- if (brw->gen < 9 && !brw->is_cherryview)
+ if (devinfo->gen < 9 && !devinfo->is_cherryview)
return false;
/* FINISHME: It should be possible to implement this optimization when there
int next_ip = 0;
/* No MRFs on Gen >= 7. */
- if (brw->gen >= 7)
+ if (devinfo->gen >= 7)
return false;
calculate_live_intervals();
if (scan_inst->mlen)
break;
- if (brw->gen == 6) {
+ if (devinfo->gen == 6) {
/* gen6 math instructions must have the destination be
* GRF, so no compute-to-MRF for them.
*/
void
fs_visitor::insert_gen4_send_dependency_workarounds()
{
- if (brw->gen != 4 || brw->is_g4x)
+ if (devinfo->gen != 4 || devinfo->is_g4x)
return;
bool progress = false;
if (inst->opcode != FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD)
continue;
- if (brw->gen >= 7) {
+ if (devinfo->gen >= 7) {
/* The offset arg before was a vec4-aligned byte offset. We need to
* turn it into a dword offset.
*/
/* We have to use a message header on Skylake to get SIMD4x2 mode.
* Reserve space for the register.
*/
- if (brw->gen >= 9) {
+ if (devinfo->gen >= 9) {
payload.reg_offset++;
alloc.sizes[payload.reg] = 2;
}
/* Do nothing but otherwise increment as normal */
} else if (dst.file == MRF &&
dst.width == 8 &&
- brw->has_compr4 &&
+ devinfo->has_compr4 &&
i + 4 < inst->sources &&
inst->src[i + 4].equals(horiz_offset(inst->src[i], 8))) {
fs_reg compr4_dst = dst;
if (inst->conditional_mod) {
fprintf(file, "%s", conditional_modifier[inst->conditional_mod]);
if (!inst->predicate &&
- (brw->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
+ (devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
inst->opcode != BRW_OPCODE_IF &&
inst->opcode != BRW_OPCODE_WHILE))) {
fprintf(file, ".f0.%d", inst->flag_subreg);
(stage == MESA_SHADER_FRAGMENT) ?
((brw_wm_prog_data*) this->prog_data)->barycentric_interp_modes : 0;
- assert(brw->gen >= 6);
+ assert(devinfo->gen >= 6);
/* R0-1: masks, pixel X/Y coordinates. */
payload.num_regs = 2;
/* R32: MSAA input coverage mask */
if (prog->SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) {
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
payload.sample_mask_in_reg = payload.num_regs;
payload.num_regs++;
if (dispatch_width == 16) {
assign_binding_table_offsets();
- if (brw->gen >= 6)
+ if (devinfo->gen >= 6)
setup_payload_gen6();
else
setup_payload_gen4();
calculate_urb_setup();
if (prog->InputsRead > 0) {
- if (brw->gen < 6)
+ if (devinfo->gen < 6)
emit_interpolation_setup_gen4();
else
emit_interpolation_setup_gen6();
* replaced with a GRF source.
*/
static bool
-could_coissue(const struct brw_context *brw, const fs_inst *inst)
+could_coissue(const struct brw_device_info *devinfo, const fs_inst *inst)
{
- if (brw->gen != 7)
+ if (devinfo->gen != 7)
return false;
switch (inst->opcode) {
foreach_block_and_inst(block, fs_inst, inst, cfg) {
ip++;
- if (!could_coissue(brw, inst) && !must_promote_imm(inst))
+ if (!could_coissue(devinfo, inst) && !must_promote_imm(inst))
continue;
for (int i = 0; i < inst->sources; i++) {
imm->inst = NULL;
imm->block = intersection;
imm->uses->push_tail(link(const_ctx, &inst->src[i]));
- imm->uses_by_coissue += could_coissue(brw, inst);
+ imm->uses_by_coissue += could_coissue(devinfo, inst);
imm->must_promote = imm->must_promote || must_promote_imm(inst);
imm->last_use_ip = ip;
} else {
imm->uses = new(const_ctx) exec_list();
imm->uses->push_tail(link(const_ctx, &inst->src[i]));
imm->val = val;
- imm->uses_by_coissue = could_coissue(brw, inst);
+ imm->uses_by_coissue = could_coissue(devinfo, inst);
imm->must_promote = must_promote_imm(inst);
imm->first_use_ip = ip;
imm->last_use_ip = ip;
if ((has_source_modifiers || entry->src.file == UNIFORM ||
!entry->src.is_contiguous()) &&
- !inst->can_do_source_mods(brw))
+ !inst->can_do_source_mods(devinfo))
return false;
if (has_source_modifiers &&
!can_change_source_types(inst))
return false;
- if (brw->gen >= 8 && (entry->src.negate || entry->src.abs) &&
+ if (devinfo->gen >= 8 && (entry->src.negate || entry->src.abs) &&
is_logic_op(inst->opcode)) {
return false;
}
val.type = inst->src[i].type;
if (inst->src[i].abs) {
- if ((brw->gen >= 8 && is_logic_op(inst->opcode)) ||
+ if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
!brw_abs_immediate(val.type, &val.fixed_hw_reg)) {
continue;
}
}
if (inst->src[i].negate) {
- if ((brw->gen >= 8 && is_logic_op(inst->opcode)) ||
+ if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
!brw_negate_immediate(val.type, &val.fixed_hw_reg)) {
continue;
}
case SHADER_OPCODE_POW:
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
- if (brw->gen < 8)
+ if (devinfo->gen < 8)
break;
/* fallthrough */
case BRW_OPCODE_BFI1:
cmp->predicate = BRW_PREDICATE_NORMAL;
cmp->flag_subreg = 1;
- if (brw->gen >= 6)
+ if (devinfo->gen >= 6)
emit_discard_jump();
}
break;
case OPCODE_MAD:
for (int i = 0; i < 4; i++) {
if (fpi->DstReg.WriteMask & (1 << i)) {
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
emit(MAD(offset(dst, i), offset(src[2], i),
offset(src[1], i), offset(src[0], i)));
} else {
case nir_intrinsic_load_sample_mask_in:
assert(v->stage == MESA_SHADER_FRAGMENT);
- assert(v->brw->gen >= 7);
+ assert(v->devinfo->gen >= 7);
reg = &v->nir_system_values[SYSTEM_VALUE_SAMPLE_MASK_IN];
if (reg->file == BAD_FILE)
*reg = fs_reg(retype(brw_vec8_grf(v->payload.sample_mask_in_reg, 0),
emit(BRW_OPCODE_ENDIF);
- if (!try_replace_with_sel() && brw->gen < 6) {
+ if (!try_replace_with_sel() && devinfo->gen < 6) {
no16("Can't support (non-uniform) control flow on SIMD16\n");
}
}
void
fs_visitor::nir_emit_loop(nir_loop *loop)
{
- if (brw->gen < 6) {
+ if (devinfo->gen < 6) {
no16("Can't support (non-uniform) control flow on SIMD16\n");
}
fs_reg tmp = vgrf(glsl_type::int_type);
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
/* Bit 15 of g0.0 is 0 if the polygon is front facing. */
fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));
break;
case nir_op_imul: {
- if (brw->gen >= 8) {
+ if (devinfo->gen >= 8) {
emit(MUL(result, op[0], op[1]));
break;
} else {
nir_const_value *value1 = nir_src_as_const_value(instr->src[1].src);
if (value0 && value0->u[0] < (1 << 16)) {
- if (brw->gen < 7) {
+ if (devinfo->gen < 7) {
emit(MUL(result, op[0], op[1]));
} else {
emit(MUL(result, op[1], op[0]));
}
break;
} else if (value1 && value1->u[0] < (1 << 16)) {
- if (brw->gen < 7) {
+ if (devinfo->gen < 7) {
emit(MUL(result, op[1], op[0]));
} else {
emit(MUL(result, op[0], op[1]));
}
}
- if (brw->gen >= 7)
+ if (devinfo->gen >= 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width), result.type);
case nir_op_imul_high:
case nir_op_umul_high: {
- if (brw->gen >= 7)
+ if (devinfo->gen >= 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width), result.type);
break;
case nir_op_uadd_carry: {
- if (brw->gen >= 7)
+ if (devinfo->gen >= 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
}
case nir_op_usub_borrow: {
- if (brw->gen >= 7)
+ if (devinfo->gen >= 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
break;
case nir_op_inot:
- if (brw->gen >= 8) {
+ if (devinfo->gen >= 8) {
resolve_source_modifiers(&op[0]);
}
emit(NOT(result, op[0]));
break;
case nir_op_ixor:
- if (brw->gen >= 8) {
+ if (devinfo->gen >= 8) {
resolve_source_modifiers(&op[0]);
resolve_source_modifiers(&op[1]);
}
emit(XOR(result, op[0], op[1]));
break;
case nir_op_ior:
- if (brw->gen >= 8) {
+ if (devinfo->gen >= 8) {
resolve_source_modifiers(&op[0]);
resolve_source_modifiers(&op[1]);
}
emit(OR(result, op[0], op[1]));
break;
case nir_op_iand:
- if (brw->gen >= 8) {
+ if (devinfo->gen >= 8) {
resolve_source_modifiers(&op[0]);
resolve_source_modifiers(&op[1]);
}
case nir_op_fmin:
case nir_op_imin:
case nir_op_umin:
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
inst = emit(BRW_OPCODE_SEL, result, op[0], op[1]);
inst->conditional_mod = BRW_CONDITIONAL_L;
} else {
case nir_op_fmax:
case nir_op_imax:
case nir_op_umax:
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
inst = emit(BRW_OPCODE_SEL, result, op[0], op[1]);
inst->conditional_mod = BRW_CONDITIONAL_GE;
} else {
/* If we need to do a boolean resolve, replace the result with -(x & 1)
* to sign extend the low bit to 0/~0
*/
- if (brw->gen <= 5 &&
+ if (devinfo->gen <= 5 &&
(instr->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) {
fs_reg masked = vgrf(glsl_type::int_type);
emit(AND(masked, result, fs_reg(1)));
cmp->predicate = BRW_PREDICATE_NORMAL;
cmp->flag_subreg = 1;
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
emit_discard_jump();
}
break;
case nir_tex_src_sampler_offset: {
/* Figure out the highest possible sampler index and mark it as used */
uint32_t max_used = sampler + instr->sampler_array_size - 1;
- if (instr->op == nir_texop_tg4 && brw->gen < 8) {
+ if (instr->op == nir_texop_tg4 && devinfo->gen < 8) {
max_used += stage_prog_data->binding_table.gather_texture_start;
} else {
max_used += stage_prog_data->binding_table.texture_start;
}
if (instr->op == nir_texop_txf_ms) {
- if (brw->gen >= 7 &&
+ if (devinfo->gen >= 7 &&
key_tex->compressed_multisample_layout_mask & (1 << sampler)) {
mcs = emit_mcs_fetch(coordinate, instr->coord_components, sampler_reg);
} else {
/* For Sandybridge with IF with embedded comparison we need to emit an
* instruction to set the flag register.
*/
- if (brw->gen == 6 && if_inst->conditional_mod) {
+ if (devinfo->gen == 6 && if_inst->conditional_mod) {
fs_inst *cmp_inst = CMP(reg_null_d, if_inst->src[0], if_inst->src[1],
if_inst->conditional_mod);
if_inst->insert_before(if_block, cmp_inst);
* in the arguments. Pre-gen6, the deltas are computed in normal
* VGRFs.
*/
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
int delta_x_arg = 0;
if (inst->src[delta_x_arg].file == HW_REG &&
inst->src[delta_x_arg].fixed_hw_reg.file ==
* The alternative would be to have per-physical-register classes, which
* would just be silly.
*/
- if (brw->intelScreen->devinfo->gen <= 5 && dispatch_width == 16) {
+ if (devinfo->gen <= 5 && dispatch_width == 16) {
/* We have to divide by 2 here because we only have even numbered
* registers. Some of the payload registers will be odd, but
* that's ok because their physical register numbers have already
int first_payload_node = node_count;
node_count += payload_node_count;
int first_mrf_hack_node = node_count;
- if (brw->gen >= 7)
+ if (devinfo->gen >= 7)
node_count += BRW_MAX_GRF - GEN7_MRF_HACK_START;
struct ra_graph *g =
ra_alloc_interference_graph(screen->wm_reg_sets[rsi].regs, node_count);
}
setup_payload_interference(g, payload_node_count, first_payload_node);
- if (brw->gen >= 7) {
+ if (devinfo->gen >= 7) {
setup_mrf_hack_interference(g, first_mrf_hack_node);
foreach_block_and_inst(block, fs_inst, inst, cfg) {
for (int i = 0; i < count / reg_size; i++) {
/* The gen7 descriptor-based offset is 12 bits of HWORD units. */
- bool gen7_read = brw->gen >= 7 && spill_offset < (1 << 12) * REG_SIZE;
+ bool gen7_read = devinfo->gen >= 7 && spill_offset < (1 << 12) * REG_SIZE;
fs_inst *unspill_inst =
new(mem_ctx) fs_inst(gen7_read ?
enum brw_predicate predicate;
bool predicate_inverse;
- if (brw->gen == 6 && if_inst->conditional_mod) {
+ if (devinfo->gen == 6 && if_inst->conditional_mod) {
/* For Sandybridge with IF with embedded comparison */
predicate = BRW_PREDICATE_NORMAL;
predicate_inverse = false;
continue;
/* Emit a CMP if our IF used the embedded comparison */
- if (brw->gen == 6 && if_inst->conditional_mod) {
+ if (devinfo->gen == 6 && if_inst->conditional_mod) {
fs_inst *cmp_inst = CMP(reg_null_d, if_inst->src[0], if_inst->src[1],
if_inst->conditional_mod);
if_inst->insert_before(block, cmp_inst);
reg = emit_sampleid_setup();
break;
case SYSTEM_VALUE_SAMPLE_MASK_IN:
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
reg = new(mem_ctx)
fs_reg(retype(brw_vec8_grf(payload.sample_mask_in_reg, 0),
BRW_REGISTER_TYPE_D));
fs_visitor::emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
const fs_reg &a)
{
- if (brw->gen < 6) {
+ if (devinfo->gen < 6) {
/* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
fs_reg y_times_a = vgrf(glsl_type::float_type);
fs_reg one_minus_a = vgrf(glsl_type::float_type);
fs_inst *inst;
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
inst->conditional_mod = conditionalmod;
} else {
fs_visitor::try_emit_mad(ir_expression *ir)
{
/* 3-src instructions were introduced in gen6. */
- if (brw->gen < 6)
+ if (devinfo->gen < 6)
return false;
/* MAD can only handle floating-point data. */
/* Deal with the real oddball stuff first */
switch (ir->operation) {
case ir_binop_add:
- if (brw->gen <= 5 && try_emit_line(ir))
+ if (devinfo->gen <= 5 && try_emit_line(ir))
return;
if (try_emit_mad(ir))
return;
return;
case ir_unop_b2f:
- if (brw->gen <= 5 && try_emit_b2f_of_comparison(ir))
+ if (devinfo->gen <= 5 && try_emit_b2f_of_comparison(ir))
return;
break;
unreachable("not reached: should be handled by ir_sub_to_add_neg");
case ir_binop_mul:
- if (brw->gen < 8 && ir->type->is_integer()) {
+ if (devinfo->gen < 8 && ir->type->is_integer()) {
/* For integer multiplication, the MUL uses the low 16 bits
* of one of the operands (src0 on gen6, src1 on gen7). The
* MACH accumulates in the contribution of the upper 16 bits
* of that operand.
*/
if (ir->operands[0]->is_uint16_constant()) {
- if (brw->gen < 7)
+ if (devinfo->gen < 7)
emit(MUL(this->result, op[0], op[1]));
else
emit(MUL(this->result, op[1], op[0]));
} else if (ir->operands[1]->is_uint16_constant()) {
- if (brw->gen < 7)
+ if (devinfo->gen < 7)
emit(MUL(this->result, op[1], op[0]));
else
emit(MUL(this->result, op[0], op[1]));
} else {
- if (brw->gen >= 7)
+ if (devinfo->gen >= 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
}
break;
case ir_binop_imul_high: {
- if (brw->gen == 7)
+ if (devinfo->gen == 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
*
* FINISHME: Don't use source modifiers on src1.
*/
- if (brw->gen >= 8) {
+ if (devinfo->gen >= 8) {
assert(mul->src[1].type == BRW_REGISTER_TYPE_D ||
mul->src[1].type == BRW_REGISTER_TYPE_UD);
if (mul->src[1].type == BRW_REGISTER_TYPE_D) {
emit_math(SHADER_OPCODE_INT_QUOTIENT, this->result, op[0], op[1]);
break;
case ir_binop_carry: {
- if (brw->gen == 7)
+ if (devinfo->gen == 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
break;
}
case ir_binop_borrow: {
- if (brw->gen == 7)
+ if (devinfo->gen == 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
case ir_binop_all_equal:
case ir_binop_nequal:
case ir_binop_any_nequal:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(ir->operands[0], &op[0]);
resolve_bool_comparison(ir->operands[1], &op[1]);
}
emit(AND(this->result, op[0], fs_reg(1)));
break;
case ir_unop_b2f:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(ir->operands[0], &op[0]);
}
op[0].type = BRW_REGISTER_TYPE_D;
}
static bool
-is_high_sampler(struct brw_context *brw, fs_reg sampler)
+is_high_sampler(const struct brw_device_info *devinfo, fs_reg sampler)
{
- if (brw->gen < 8 && !brw->is_haswell)
+ if (devinfo->gen < 8 && !devinfo->is_haswell)
return false;
return sampler.file != IMM || sampler.fixed_hw_reg.dw1.ud >= 16;
int length = 0;
if (op == ir_tg4 || offset_value.file != BAD_FILE ||
- is_high_sampler(brw, sampler)) {
+ is_high_sampler(devinfo, sampler)) {
/* For general texture offsets (no txf workaround), we need a header to
* put them in. Note that for SIMD16 we're making space for two actual
* hardware registers here, so the emit will have to fix up for this.
coordinate = offset(coordinate, 1);
length++;
- if (brw->gen >= 9) {
+ if (devinfo->gen >= 9) {
if (coord_components >= 2) {
emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), coordinate));
coordinate = offset(coordinate, 1);
emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), lod));
length++;
- for (int i = brw->gen >= 9 ? 2 : 1; i < coord_components; i++) {
+ for (int i = devinfo->gen >= 9 ? 2 : 1; i < coord_components; i++) {
emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), coordinate));
coordinate = offset(coordinate, 1);
length++;
* tracking to get the scaling factor.
*/
if (is_rect &&
- (brw->gen < 6 ||
- (brw->gen >= 6 && (key_tex->gl_clamp_mask[0] & (1 << sampler) ||
- key_tex->gl_clamp_mask[1] & (1 << sampler))))) {
+ (devinfo->gen < 6 ||
+ (devinfo->gen >= 6 && (key_tex->gl_clamp_mask[0] & (1 << sampler) ||
+ key_tex->gl_clamp_mask[1] & (1 << sampler))))) {
struct gl_program_parameter_list *params = prog->Parameters;
int tokens[STATE_LENGTH] = {
STATE_INTERNAL,
* texture coordinates. We use the program parameter state
* tracking to get the scaling factor.
*/
- if (brw->gen < 6 && is_rect) {
+ if (devinfo->gen < 6 && is_rect) {
fs_reg dst = fs_reg(GRF, alloc.allocate(coord_components));
fs_reg src = coordinate;
coordinate = dst;
*/
fs_reg dst = vgrf(glsl_type::get_instance(dest_type->base_type, 4, 1));
- if (brw->gen >= 7) {
+ if (devinfo->gen >= 7) {
inst = emit_texture_gen7(op, dst, coordinate, coord_components,
shadow_c, lod, lod2, grad_components,
sample_index, mcs, sampler_reg,
offset_value);
- } else if (brw->gen >= 5) {
+ } else if (devinfo->gen >= 5) {
inst = emit_texture_gen5(op, dst, coordinate, coord_components,
shadow_c, lod, lod2, grad_components,
sample_index, sampler,
inst->offset |=
gather_channel(gather_component, sampler) << 16; /* M0.2:16-17 */
- if (brw->gen == 6)
+ if (devinfo->gen == 6)
emit_gen6_gather_wa(key_tex->gen6_gather_wa[sampler], dst);
}
->array->type->array_size();
uint32_t max_used = sampler + array_size - 1;
- if (ir->op == ir_tg4 && brw->gen < 8) {
+ if (ir->op == ir_tg4 && devinfo->gen < 8) {
max_used += stage_prog_data->binding_table.gather_texture_start;
} else {
max_used += stage_prog_data->binding_table.texture_start;
ir->lod_info.sample_index->accept(this);
sample_index = this->result;
- if (brw->gen >= 7 &&
+ if (devinfo->gen >= 7 &&
key_tex->compressed_multisample_layout_mask & (1 << sampler)) {
mcs = emit_mcs_fetch(coordinate, ir->coordinate->type->vector_elements,
sampler_reg);
cmp->predicate = BRW_PREDICATE_NORMAL;
cmp->flag_subreg = 1;
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
emit_discard_jump();
}
}
break;
case ir_binop_logic_xor:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
fs_reg temp = vgrf(expr->type);
emit(XOR(temp, op[0], op[1]));
inst = emit(AND(reg_null_d, temp, fs_reg(1)));
break;
case ir_binop_logic_or:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
fs_reg temp = vgrf(expr->type);
emit(OR(temp, op[0], op[1]));
inst = emit(AND(reg_null_d, temp, fs_reg(1)));
break;
case ir_binop_logic_and:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
fs_reg temp = vgrf(expr->type);
emit(AND(temp, op[0], op[1]));
inst = emit(AND(reg_null_d, temp, fs_reg(1)));
break;
case ir_unop_f2b:
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
emit(CMP(reg_null_d, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ));
} else {
inst = emit(MOV(reg_null_f, op[0]));
break;
case ir_unop_i2b:
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
} else {
inst = emit(MOV(reg_null_d, op[0]));
case ir_binop_all_equal:
case ir_binop_nequal:
case ir_binop_any_nequal:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(expr->operands[0], &op[0]);
resolve_bool_comparison(expr->operands[1], &op[1]);
}
case ir_binop_all_equal:
case ir_binop_nequal:
case ir_binop_any_nequal:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(expr->operands[0], &op[0]);
resolve_bool_comparison(expr->operands[1], &op[1]);
}
dst.type = BRW_REGISTER_TYPE_D;
fs_reg tmp = vgrf(glsl_type::int_type);
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
/* Bit 15 of g0.0 is 0 if the polygon is front facing. */
fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));
*/
this->base_ir = ir->condition;
- if (brw->gen == 6) {
+ if (devinfo->gen == 6) {
emit_if_gen6(ir);
} else {
emit_bool_to_cond_code(ir->condition);
emit(BRW_OPCODE_ENDIF);
- if (!try_replace_with_sel() && brw->gen < 6) {
+ if (!try_replace_with_sel() && devinfo->gen < 6) {
no16("Can't support (non-uniform) control flow on SIMD16\n");
}
}
void
fs_visitor::visit(ir_loop *ir)
{
- if (brw->gen < 6) {
+ if (devinfo->gen < 6) {
no16("Can't support (non-uniform) control flow on SIMD16\n");
}
fs_inst *write;
write = emit(FS_OPCODE_FB_WRITE);
write->eot = true;
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
write->base_mrf = 2;
write->mlen = 4 * reg_width;
} else {
* varying to avoid GPU hangs, so set that.
*/
brw_wm_prog_data *wm_prog_data = (brw_wm_prog_data *) this->prog_data;
- wm_prog_data->num_varying_inputs = brw->gen < 6 ? 1 : 0;
+ wm_prog_data->num_varying_inputs = devinfo->gen < 6 ? 1 : 0;
memset(wm_prog_data->urb_setup, -1,
sizeof(wm_prog_data->urb_setup[0]) * VARYING_SLOT_MAX);
const fs_reg xstart(negate(brw_vec1_grf(1, 0)));
const fs_reg ystart(negate(brw_vec1_grf(1, 1)));
- if (brw->has_pln && dispatch_width == 16) {
+ if (devinfo->has_pln && dispatch_width == 16) {
emit(ADD(half(offset(delta_xy, 0), 0), half(this->pixel_x, 0), xstart));
emit(ADD(half(offset(delta_xy, 0), 1), half(this->pixel_y, 0), ystart));
emit(ADD(half(offset(delta_xy, 1), 0), half(this->pixel_x, 1), xstart))
colors_enabled = (1 << components) - 1;
}
- if (dispatch_width == 8 || (brw->gen >= 6 && !do_dual_src)) {
+ if (dispatch_width == 8 || (devinfo->gen >= 6 && !do_dual_src)) {
/* SIMD8 write looks like:
* m + 0: r0
* m + 1: r1
len++;
}
return len;
- } else if (brw->gen >= 6 && do_dual_src) {
+ } else if (devinfo->gen >= 6 && do_dual_src) {
/* SIMD16 dual source blending for gen6+.
*
* From the SNB PRM, volume 4, part 1, page 193:
* dispatched. This field is only required for the end-of-
* thread message and on all dual-source messages."
*/
- if (brw->gen >= 6 &&
- (brw->is_haswell || brw->gen >= 8 || !prog_data->uses_kill) &&
+ if (devinfo->gen >= 6 &&
+ (devinfo->is_haswell || devinfo->gen >= 8 || !prog_data->uses_kill) &&
color1.file == BAD_FILE &&
key->nr_color_regions == 1) {
header_present = false;
}
if (source_depth_to_render_target) {
- if (brw->gen == 6) {
+ if (devinfo->gen == 6) {
/* For outputting oDepth on gen6, SIMD8 writes have to be
* used. This would require SIMD8 moves of each half to
* message regs, kind of like pre-gen5 SIMD16 FB writes.
fs_inst *load;
fs_inst *write;
- if (brw->gen >= 7) {
+ if (devinfo->gen >= 7) {
/* Send from the GRF */
fs_reg payload = fs_reg(GRF, -1, BRW_REGISTER_TYPE_F);
load = emit(LOAD_PAYLOAD(payload, sources, length));
"FB write target %d",
target);
fs_reg src0_alpha;
- if (brw->gen >= 6 && key->replicate_alpha && target != 0)
+ if (devinfo->gen >= 6 && key->replicate_alpha && target != 0)
src0_alpha = offset(outputs[0], 3);
inst = emit_single_fb_write(this->outputs[target], reg_undef,
void
fs_visitor::resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg)
{
- assert(brw->gen <= 5);
+ assert(devinfo->gen <= 5);
if (rvalue->type != glsl_type::bool_type)
return;
this->source_depth_to_render_target = false;
this->runtime_check_aads_emit = false;
this->first_non_payload_grf = 0;
- this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
+ this->max_grf = devinfo->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
this->current_annotation = NULL;
this->base_ir = NULL;
bool is_send_from_grf() const;
bool is_partial_write() const;
int regs_read(int arg) const;
- bool can_do_source_mods(struct brw_context *brw);
+ bool can_do_source_mods(const struct brw_device_info *devinfo);
bool has_side_effects() const;
bool reads_flag() const;
unsigned regs_read(unsigned arg) const;
bool can_reswizzle(int dst_writemask, int swizzle, int swizzle_mask);
void reswizzle(int dst_writemask, int swizzle);
- bool can_do_source_mods(struct brw_context *brw);
+ bool can_do_source_mods(const struct brw_device_info *devinfo);
bool reads_flag()
{
struct brw_stage_prog_data *stage_prog_data,
gl_shader_stage stage)
: brw(brw),
+ devinfo(brw->intelScreen->devinfo),
ctx(&brw->ctx),
shader(shader_prog ?
(struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
}
if (prog->UsesGather) {
- if (brw->gen >= 8) {
+ if (devinfo->gen >= 8) {
stage_prog_data->binding_table.gather_texture_start =
stage_prog_data->binding_table.texture_start;
} else {
public:
struct brw_context * const brw;
+ const struct brw_device_info * const devinfo;
struct gl_context * const ctx;
struct brw_shader * const shader;
struct gl_shader_program * const shader_prog;
}
bool
-vec4_instruction::can_do_source_mods(struct brw_context *brw)
+vec4_instruction::can_do_source_mods(const struct brw_device_info *devinfo)
{
- if (brw->gen == 6 && is_math())
+ if (devinfo->gen == 6 && is_math())
return false;
if (is_send_from_grf())
* multiply, DepCtrl must not be used."
* May apply to future SoCs as well.
*/
- if (brw->is_cherryview) {
+ if (devinfo->is_cherryview) {
if (inst->opcode == BRW_OPCODE_MUL &&
IS_DWORD(inst->src[0]) &&
IS_DWORD(inst->src[1]))
}
#undef IS_DWORD
- if (brw->gen >= 8) {
+ if (devinfo->gen >= 8) {
if (inst->opcode == BRW_OPCODE_F32TO16)
return true;
}
if (scan_inst->mlen)
break;
- if (brw->gen == 6) {
+ if (devinfo->gen == 6) {
/* gen6 math instructions must have the destination be
* GRF, so no compute-to-MRF for them.
*/
if (inst->conditional_mod) {
fprintf(file, "%s", conditional_modifier[inst->conditional_mod]);
if (!inst->predicate &&
- (brw->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
- inst->opcode != BRW_OPCODE_IF &&
- inst->opcode != BRW_OPCODE_WHILE))) {
+ (devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
+ inst->opcode != BRW_OPCODE_IF &&
+ inst->opcode != BRW_OPCODE_WHILE))) {
fprintf(file, ".f0.%d", inst->flag_subreg);
}
}
unsigned vue_entries =
MAX2(nr_attributes, prog_data->vue_map.num_slots);
- if (brw->gen == 6)
+ if (devinfo->gen == 6)
prog_data->urb_entry_size = ALIGN(vue_entries, 8) / 8;
else
prog_data->urb_entry_size = ALIGN(vue_entries, 4) / 4;
/* The pre-gen6 VS requires that some push constants get loaded no
* matter what, or the GPU would hang.
*/
- if (brw->gen < 6 && this->uniforms == 0) {
+ if (devinfo->gen < 6 && this->uniforms == 0) {
assert(this->uniforms < this->uniform_array_size);
this->uniform_vector_size[this->uniforms] = 1;
src_reg
vec4_visitor::get_timestamp()
{
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
src_reg ts = src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
BRW_ARF_TIMESTAMP,
}
static bool
-try_constant_propagate(struct brw_context *brw, vec4_instruction *inst,
+try_constant_propagate(const struct brw_device_info *devinfo,
+ vec4_instruction *inst,
int arg, struct copy_entry *entry)
{
/* For constant propagation, we only handle the same constant
}
if (inst->src[arg].abs) {
- if ((brw->gen >= 8 && is_logic_op(inst->opcode)) ||
+ if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
!brw_abs_immediate(value.type, &value.fixed_hw_reg)) {
return false;
}
}
if (inst->src[arg].negate) {
- if ((brw->gen >= 8 && is_logic_op(inst->opcode)) ||
+ if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
!brw_negate_immediate(value.type, &value.fixed_hw_reg)) {
return false;
}
case SHADER_OPCODE_POW:
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
- if (brw->gen < 8)
+ if (devinfo->gen < 8)
break;
/* fallthrough */
case BRW_OPCODE_DP2:
}
static bool
-try_copy_propagate(struct brw_context *brw, vec4_instruction *inst,
+try_copy_propagate(const struct brw_device_info *devinfo,
+ vec4_instruction *inst,
int arg, struct copy_entry *entry)
{
/* For constant propagation, we only handle the same constant
value.file != ATTR)
return false;
- if (brw->gen >= 8 && (value.negate || value.abs) &&
+ if (devinfo->gen >= 8 && (value.negate || value.abs) &&
is_logic_op(inst->opcode)) {
return false;
}
* instructions.
*/
if ((has_source_modifiers || value.file == UNIFORM ||
- value.swizzle != BRW_SWIZZLE_XYZW) && !inst->can_do_source_mods(brw))
+ value.swizzle != BRW_SWIZZLE_XYZW) && !inst->can_do_source_mods(devinfo))
return false;
if (has_source_modifiers && value.type != inst->src[arg].type)
if (c != 4)
continue;
- if (do_constant_prop && try_constant_propagate(brw, inst, i, &entry))
+ if (do_constant_prop && try_constant_propagate(devinfo, inst, i, &entry))
progress = true;
- if (try_copy_propagate(brw, inst, i, &entry))
+ if (try_copy_propagate(devinfo, inst, i, &entry))
progress = true;
}
using namespace brw;
static bool
-can_do_writemask(const struct brw_context *brw,
+can_do_writemask(const struct brw_device_info *devinfo,
const vec4_instruction *inst)
{
switch (inst->opcode) {
/* The MATH instruction on Gen6 only executes in align1 mode, which does
* not support writemasking.
*/
- if (brw->gen == 6 && inst->is_math())
+ if (devinfo->gen == 6 && inst->is_math())
return false;
if (inst->is_tex())
/* If the instruction can't do writemasking, then it's all or
* nothing.
*/
- if (!can_do_writemask(brw, inst)) {
+ if (!can_do_writemask(devinfo, inst)) {
bool result = result_live[0] | result_live[1] |
result_live[2] | result_live[3];
result_live[0] = result;
/* We need to increment Global Offset by 1 to make room for Broadwell's
* extra "Vertex Count" payload at the beginning of the URB entry.
*/
- if (brw->gen >= 8)
+ if (devinfo->gen >= 8)
inst->offset++;
inst->urb_write_flags = BRW_URB_WRITE_PER_SLOT_OFFSET;
* URB entry. Since this is an OWord message, Global Offset is counted
* in 128-bit units, so we must set it to 2.
*/
- if (brw->gen >= 8)
+ if (devinfo->gen >= 8)
inst->offset = 2;
inst->base_mrf = base_mrf;
inst->mlen = 2;
vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
const src_reg &src1, const src_reg &src2) \
{ \
- assert(brw->gen >= 6); \
+ assert(devinfo->gen >= 6); \
return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
src0, src1, src2); \
}
vec4_visitor::IF(src_reg src0, src_reg src1,
enum brw_conditional_mod condition)
{
- assert(brw->gen == 6);
+ assert(devinfo->gen == 6);
vec4_instruction *inst;
src_reg
vec4_visitor::fix_math_operand(src_reg src)
{
- if (brw->gen < 6 || brw->gen >= 8 || src.file == BAD_FILE)
+ if (devinfo->gen < 6 || devinfo->gen >= 8 || src.file == BAD_FILE)
return src;
/* The gen6 math instruction ignores the source modifiers --
* can't use.
*/
- if (brw->gen == 7 && src.file != IMM)
+ if (devinfo->gen == 7 && src.file != IMM)
return src;
dst_reg expanded = dst_reg(this, glsl_type::vec4_type);
vec4_instruction *math =
emit(opcode, dst, fix_math_operand(src0), fix_math_operand(src1));
- if (brw->gen == 6 && dst.writemask != WRITEMASK_XYZW) {
+ if (devinfo->gen == 6 && dst.writemask != WRITEMASK_XYZW) {
/* MATH on Gen6 must be align1, so we can't do writemasks. */
math->dst = dst_reg(this, glsl_type::vec4_type);
math->dst.type = dst.type;
emit(MOV(dst, src_reg(math->dst)));
- } else if (brw->gen < 6) {
+ } else if (devinfo->gen < 6) {
math->base_mrf = 1;
math->mlen = src1.file == BAD_FILE ? 1 : 2;
}
void
vec4_visitor::emit_pack_half_2x16(dst_reg dst, src_reg src0)
{
- if (brw->gen < 7) {
+ if (devinfo->gen < 7) {
unreachable("ir_unop_pack_half_2x16 should be lowered");
}
void
vec4_visitor::emit_unpack_half_2x16(dst_reg dst, src_reg src0)
{
- if (brw->gen < 7) {
+ if (devinfo->gen < 7) {
unreachable("ir_unop_unpack_half_2x16 should be lowered");
}
break;
case ir_binop_logic_xor:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
src_reg temp = src_reg(this, ir->type);
emit(XOR(dst_reg(temp), op[0], op[1]));
inst = emit(AND(dst_null_d(), temp, src_reg(1)));
break;
case ir_binop_logic_or:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
src_reg temp = src_reg(this, ir->type);
emit(OR(dst_reg(temp), op[0], op[1]));
inst = emit(AND(dst_null_d(), temp, src_reg(1)));
break;
case ir_binop_logic_and:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
src_reg temp = src_reg(this, ir->type);
emit(AND(dst_reg(temp), op[0], op[1]));
inst = emit(AND(dst_null_d(), temp, src_reg(1)));
break;
case ir_unop_f2b:
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
emit(CMP(dst_null_d(), op[0], src_reg(0.0f), BRW_CONDITIONAL_NZ));
} else {
inst = emit(MOV(dst_null_f(), op[0]));
break;
case ir_unop_i2b:
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
emit(CMP(dst_null_d(), op[0], src_reg(0), BRW_CONDITIONAL_NZ));
} else {
inst = emit(MOV(dst_null_d(), op[0]));
break;
case ir_binop_all_equal:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(expr->operands[0], &op[0]);
resolve_bool_comparison(expr->operands[1], &op[1]);
}
break;
case ir_binop_any_nequal:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(expr->operands[0], &op[0]);
resolve_bool_comparison(expr->operands[1], &op[1]);
}
break;
case ir_unop_any:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(expr->operands[0], &op[0]);
}
inst = emit(CMP(dst_null_d(), op[0], src_reg(0), BRW_CONDITIONAL_NZ));
case ir_binop_lequal:
case ir_binop_equal:
case ir_binop_nequal:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(expr->operands[0], &op[0]);
resolve_bool_comparison(expr->operands[1], &op[1]);
}
vec4_visitor::try_emit_mad(ir_expression *ir)
{
/* 3-src instructions were introduced in gen6. */
- if (brw->gen < 6)
+ if (devinfo->gen < 6)
return false;
/* MAD can only handle floating-point data. */
* false. Early hardware only sets the least significant bit, and
* leaves the other bits undefined. So we can't use it.
*/
- if (brw->gen < 6)
+ if (devinfo->gen < 6)
return false;
ir_expression *const cmp = ir->operands[0]->as_expression();
{
vec4_instruction *inst;
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
inst->conditional_mod = conditionalmod;
} else {
vec4_visitor::emit_lrp(const dst_reg &dst,
const src_reg &x, const src_reg &y, const src_reg &a)
{
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
/* Note that the instruction's argument order is reversed from GLSL
* and the IR.
*/
vec4_instruction *pull;
- if (brw->gen >= 9) {
+ if (devinfo->gen >= 9) {
/* Gen9+ needs a message header in order to use SIMD4x2 mode */
src_reg header(this, glsl_type::uvec4_type, 2);
header);
pull->mlen = 2;
pull->header_present = true;
- } else if (brw->gen >= 7) {
+ } else if (devinfo->gen >= 7) {
dst_reg grf_offset = dst_reg(this, glsl_type::int_type);
grf_offset.type = offset_reg.type;
unreachable("not reached: should be handled by ir_sub_to_add_neg");
case ir_binop_mul:
- if (brw->gen < 8 && ir->type->is_integer()) {
+ if (devinfo->gen < 8 && ir->type->is_integer()) {
/* For integer multiplication, the MUL uses the low 16 bits of one of
* the operands (src0 through SNB, src1 on IVB and later). The MACH
* accumulates in the contribution of the upper 16 bits of that
* 16 bits, though, we can just emit a single MUL.
*/
if (ir->operands[0]->is_uint16_constant()) {
- if (brw->gen < 7)
+ if (devinfo->gen < 7)
emit(MUL(result_dst, op[0], op[1]));
else
emit(MUL(result_dst, op[1], op[0]));
} else if (ir->operands[1]->is_uint16_constant()) {
- if (brw->gen < 7)
+ if (devinfo->gen < 7)
emit(MUL(result_dst, op[1], op[0]));
else
emit(MUL(result_dst, op[0], op[1]));
case ir_binop_gequal:
case ir_binop_equal:
case ir_binop_nequal: {
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(ir->operands[0], &op[0]);
resolve_bool_comparison(ir->operands[1], &op[1]);
}
}
case ir_binop_all_equal:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(ir->operands[0], &op[0]);
resolve_bool_comparison(ir->operands[1], &op[1]);
}
}
break;
case ir_binop_any_nequal:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(ir->operands[0], &op[0]);
resolve_bool_comparison(ir->operands[1], &op[1]);
}
break;
case ir_unop_any:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(ir->operands[0], &op[0]);
}
emit(CMP(dst_null_d(), op[0], src_reg(0), BRW_CONDITIONAL_NZ));
emit(AND(result_dst, op[0], src_reg(1)));
break;
case ir_unop_b2f:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(ir->operands[0], &op[0]);
}
op[0].type = BRW_REGISTER_TYPE_D;
}
if (const_offset_ir) {
- if (brw->gen >= 8) {
+ if (devinfo->gen >= 8) {
/* Store the offset in a GRF so we can send-from-GRF. */
offset = src_reg(this, glsl_type::int_type);
emit(MOV(dst_reg(offset), src_reg(const_offset / 16)));
}
static bool
-is_high_sampler(struct brw_context *brw, src_reg sampler)
+is_high_sampler(const struct brw_device_info *devinfo, src_reg sampler)
{
- if (brw->gen < 8 && !brw->is_haswell)
+ if (devinfo->gen < 8 && !devinfo->is_haswell)
return false;
return sampler.file != IMM || sampler.fixed_hw_reg.dw1.ud >= 16;
->array->type->array_size();
uint32_t max_used = sampler + array_size - 1;
- if (ir->op == ir_tg4 && brw->gen < 8) {
+ if (ir->op == ir_tg4 && devinfo->gen < 8) {
max_used += prog_data->base.binding_table.gather_texture_start;
} else {
max_used += prog_data->base.binding_table.texture_start;
sample_index = this->result;
sample_index_type = ir->lod_info.sample_index->type;
- if (brw->gen >= 7 && key->tex.compressed_multisample_layout_mask & (1<<sampler))
+ if (devinfo->gen >= 7 && key->tex.compressed_multisample_layout_mask & (1<<sampler))
mcs = emit_mcs_fetch(ir, coordinate, sampler_reg);
else
mcs = src_reg(0u);
* - Sampler indices too large to fit in a 4-bit value.
*/
inst->header_present =
- brw->gen < 5 || brw->gen >= 9 ||
+ devinfo->gen < 5 || devinfo->gen >= 9 ||
inst->offset != 0 || ir->op == ir_tg4 ||
- is_high_sampler(brw, sampler_reg);
+ is_high_sampler(devinfo, sampler_reg);
inst->base_mrf = 2;
inst->mlen = inst->header_present + 1; /* always at least one */
inst->dst.writemask = WRITEMASK_XYZW;
int param_base = inst->base_mrf + inst->header_present;
if (ir->op == ir_txs || ir->op == ir_query_levels) {
- int writemask = brw->gen == 4 ? WRITEMASK_W : WRITEMASK_X;
+ int writemask = devinfo->gen == 4 ? WRITEMASK_W : WRITEMASK_X;
emit(MOV(dst_reg(MRF, param_base, lod_type, writemask), lod));
} else {
/* Load the coordinate */
/* Load the LOD info */
if (ir->op == ir_tex || ir->op == ir_txl) {
int mrf, writemask;
- if (brw->gen >= 5) {
+ if (devinfo->gen >= 5) {
mrf = param_base + 1;
if (ir->shadow_comparitor) {
writemask = WRITEMASK_Y;
writemask = WRITEMASK_X;
inst->mlen++;
}
- } else /* brw->gen == 4 */ {
+ } else /* devinfo->gen == 4 */ {
mrf = param_base;
writemask = WRITEMASK_W;
}
} else if (ir->op == ir_txf_ms) {
emit(MOV(dst_reg(MRF, param_base + 1, sample_index_type, WRITEMASK_X),
sample_index));
- if (brw->gen >= 7) {
+ if (devinfo->gen >= 7) {
/* MCS data is in the first channel of `mcs`, but we need to get it into
* the .y channel of the second vec4 of params, so replicate .x across
* the whole vec4 and then mask off everything except .y
} else if (ir->op == ir_txd) {
const glsl_type *type = lod_type;
- if (brw->gen >= 5) {
+ if (devinfo->gen >= 5) {
dPdx.swizzle = BRW_SWIZZLE4(SWIZZLE_X,SWIZZLE_X,SWIZZLE_Y,SWIZZLE_Y);
dPdy.swizzle = BRW_SWIZZLE4(SWIZZLE_X,SWIZZLE_X,SWIZZLE_Y,SWIZZLE_Y);
emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_XZ), dPdx));
shadow_comparitor));
}
}
- } else /* brw->gen == 4 */ {
+ } else /* devinfo->gen == 4 */ {
emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_XYZ), dPdx));
emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_XYZ), dPdy));
inst->mlen += 2;
}
}
- if (brw->gen == 6 && ir->op == ir_tg4) {
+ if (devinfo->gen == 6 && ir->op == ir_tg4) {
emit_gen6_gather_wa(key->tex.gen6_gather_wa[sampler], inst->dst);
}
*/
this->base_ir = ir->condition;
- if (brw->gen == 6) {
+ if (devinfo->gen == 6) {
emit_if_gen6(ir);
} else {
enum brw_predicate predicate;
void
vec4_visitor::emit_psiz_and_flags(dst_reg reg)
{
- if (brw->gen < 6 &&
+ if (devinfo->gen < 6 &&
((prog_data->vue_map.slots_valid & VARYING_BIT_PSIZ) ||
- key->userclip_active || brw->has_negative_rhw_bug)) {
+ key->userclip_active || devinfo->has_negative_rhw_bug)) {
dst_reg header1 = dst_reg(this, glsl_type::uvec4_type);
dst_reg header1_w = header1;
header1_w.writemask = WRITEMASK_W;
* Later, clipping will detect ucp[6] and ensure the primitive is
* clipped against all fixed planes.
*/
- if (brw->has_negative_rhw_bug) {
+ if (devinfo->has_negative_rhw_bug) {
src_reg ndc_w = src_reg(output_reg[BRW_VARYING_SLOT_NDC]);
ndc_w.swizzle = BRW_SWIZZLE_WWWW;
emit(CMP(dst_null_f(), ndc_w, src_reg(0.0f), BRW_CONDITIONAL_L));
}
emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), src_reg(header1)));
- } else if (brw->gen < 6) {
+ } else if (devinfo->gen < 6) {
emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), 0u));
} else {
emit(MOV(retype(reg, BRW_REGISTER_TYPE_D), src_reg(0)));
}
static int
-align_interleaved_urb_mlen(struct brw_context *brw, int mlen)
+align_interleaved_urb_mlen(const struct brw_device_info *devinfo, int mlen)
{
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
/* URB data written (does not include the message header reg) must
* be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
* section 5.4.3.2.2: URB_INTERLEAVED.
*/
emit_urb_write_header(mrf++);
- if (brw->gen < 6) {
+ if (devinfo->gen < 6) {
emit_ndc_computation();
}
current_annotation = "URB write";
vec4_instruction *inst = emit_urb_write_opcode(complete);
inst->base_mrf = base_mrf;
- inst->mlen = align_interleaved_urb_mlen(brw, mrf - base_mrf);
+ inst->mlen = align_interleaved_urb_mlen(devinfo, mrf - base_mrf);
inst->offset += offset;
} while(!complete);
}
/* Pre-gen6, the message header uses byte offsets instead of vec4
* (16-byte) offset units.
*/
- if (brw->gen < 6)
+ if (devinfo->gen < 6)
message_header_scale *= 16;
if (reladdr) {
/* Pre-gen6, the message header uses byte offsets instead of vec4
* (16-byte) offset units.
*/
- if (brw->gen < 6) {
+ if (devinfo->gen < 6) {
emit_before(block, inst, MUL(dst_reg(index), index, src_reg(16)));
}
return index;
- } else if (brw->gen >= 8) {
+ } else if (devinfo->gen >= 8) {
/* Store the offset in a GRF so we can send-from-GRF. */
src_reg offset = src_reg(this, glsl_type::int_type);
emit_before(block, inst, MOV(dst_reg(offset), src_reg(reg_offset)));
return offset;
} else {
- int message_header_scale = brw->gen < 6 ? 16 : 1;
+ int message_header_scale = devinfo->gen < 6 ? 16 : 1;
return src_reg(reg_offset * message_header_scale);
}
}
void
vec4_visitor::resolve_bool_comparison(ir_rvalue *rvalue, src_reg *reg)
{
- assert(brw->gen <= 5);
+ assert(devinfo->gen <= 5);
if (!rvalue->type->is_boolean())
return;
this->virtual_grf_end = NULL;
this->live_intervals = NULL;
- this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
+ this->max_grf = devinfo->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
this->uniforms = 0;
break;
case OPCODE_ARL:
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
dst.writemask = WRITEMASK_X;
dst_reg dst_f = dst;
dst_f.type = BRW_REGISTER_TYPE_F;
dst_reladdr.writemask = WRITEMASK_X;
emit(ADD(dst_reladdr, this->vp_addr_reg, src_reg(src.Index)));
- if (brw->gen < 6)
+ if (devinfo->gen < 6)
emit(MUL(dst_reladdr, reladdr, src_reg(16)));
#if 0
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