Make pylint happy.

diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py
index 3f87d2697e39c4d0c0225d3099fe26764d18dfb7..09bab1d05017289233d626f0d4cc341dde2d8256 100644 (file)
--- a/debug/targets/RISC-V/spike32-2.py
+++ b/debug/targets/RISC-V/spike32-2.py
@@ -1,7 +1,7 @@
 import targets
 import testlib
 
-import spike32
+import spike32  # pylint: disable=import-error
 
 class spike32_2(targets.Target):
     harts = [spike32.spike32_hart(), spike32.spike32_hart()]

diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py
index e1df6d235889330b016c645280ef23fe4222af17..f2e0a8a7af89cc190b432f6a94b3b3400711fbfe 100644 (file)
--- a/debug/targets/RISC-V/spike64-2.py
+++ b/debug/targets/RISC-V/spike64-2.py
@@ -1,7 +1,7 @@
 import targets
 import testlib
 
-import spike64
+import spike64  # pylint: disable=import-error
 
 class spike64_2(targets.Target):
     harts = [spike64.spike64_hart(), spike64.spike64_hart()]

diff --git a/debug/targets/SiFive/Freedom/U500Sim.py b/debug/targets/SiFive/Freedom/U500Sim.py
index 5c500c4842c7a6009a5dca06576d72a19843a133..065ab08ae446b4fb76dba6b9a4968acec34b464c 100644 (file)
--- a/debug/targets/SiFive/Freedom/U500Sim.py
+++ b/debug/targets/SiFive/Freedom/U500Sim.py
@@ -8,7 +8,7 @@ class U500Hart(targets.Hart):
     instruction_hardware_breakpoint_count = 2
     link_script_path = "Freedom.lds"
 
-class U500Sim(Target):
+class U500Sim(targets.Target):
     timeout_sec = 6000
     openocd_config_path = "Freedom.cfg"
     harts = [U500Hart()]