soc: use set

diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py
index babd6624c9cf5a313c3bc8204475f746a585c09f..52e93dd8723024a84368e4568d857c90bcd74008 100644 (file)
--- a/misoclib/soc/__init__.py
+++ b/misoclib/soc/__init__.py
@@ -160,7 +160,7 @@ class SoC(Module):
                return self._csr_regions
 
        def do_finalize(self):
-               registered_mems = [regions[0] for regions in self._memory_regions]
+               registered_mems = {regions[0] for regions in self._memory_regions}
                if self.cpu_type != "none":
                        for mem in "rom", "sram":
                                if mem not in registered_mems: