if (rn < NUM_VIF_REGS)
{
- if (rn < NUM_VIF_REGS-1)
+ if (rn < NUM_VIF_REGS-2)
return read_pke_reg (&pke0_device, rn, memory);
- else
+ else if (rn == NUM_VIF_REGS-2)
return read_pke_pc (&pke0_device, memory);
+ else
+ return read_pke_pcx (&pke0_device, memory);
}
rn -= NUM_VIF_REGS; /* VIF1 registers are last */
if (rn < NUM_VIF_REGS)
{
- if (rn < NUM_VIF_REGS-1)
+ if (rn < NUM_VIF_REGS-2)
return read_pke_reg (&pke1_device, rn, memory);
- else
+ else if (rn == NUM_VIF_REGS-2)
return read_pke_pc (&pke1_device, memory);
+ else
+ return read_pke_pcx (&pke1_device, memory);
}
sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
#define NUM_VU_REGS 153
#define NUM_VU_INTEGER_REGS 16
-#define NUM_VIF_REGS 25
+#define NUM_VIF_REGS 26
#define FIRST_VEC_REG 25
#define NUM_R5900_REGS 128
void sky_sim_engine_halt PARAMS ((SIM_DESC sd, sim_cpu *last, sim_cia cia));
#define SIM_ENGINE_HALT_HOOK(sd, last, cia) sky_sim_engine_halt(sd, last, cia);
+#ifdef SIM_ENGINE_RESTART_HOOK
+#undef SIM_ENGINE_RESTART_HOOK
+#endif
+
+void sky_sim_engine_restart PARAMS ((SIM_DESC sd, sim_cpu *last, sim_cia cia));
+#define SIM_ENGINE_RESTART_HOOK(sd, L, pc) sky_sim_engine_restart(sd, L, pc);
+
#ifndef TM_TXVU_H /* In case GDB hasn't been configured yet */
enum txvu_cpu_context
{
/* Memory address containing last device to execute */
#define LAST_DEVICE GDB_COMM_AREA
-#define BREAK_MASK 0x02 /* Breakpoint bit is #57 */
+/* The FIFO breakpoint count and table */
+#define FIFO_BPT_CNT (GDB_COMM_AREA + 4)
+#define FIFO_BPT_TBL (GDB_COMM_AREA + 8)
+
+#define TXVU_VU_BRK_MASK 0x02 /* Breakpoint bit is #57 for VU insns */
+#define TXVU_VIF_BRK_MASK 0x0f /* Breakpoint opcode for VIF insns */
+
#endif /* !TM_TXVU_H */
#endif /* TARGET_SKY */
/* end-sanitize-sky */
}
-/* Read PKE Pseudo-PC into buf in target order */
+/* Read PKE Pseudo-PC index into buf in target order */
int
-read_pke_pc (struct pke_device *me, void *buf)
+read_pke_pcx (struct pke_device *me, void *buf)
{
*((int *) buf) = H2T_4( (me->fifo_pc << 2) | me->qw_pc );
return 4;
}
+/* Read PKE Pseudo-PC source address into buf in target order */
+int
+read_pke_pc (struct pke_device *me, void *buf)
+{
+ struct fifo_quadword* fqw = pke_fifo_access(& me->fifo, me->fifo_pc);
+ unsigned_4 addr;
+
+ if (fqw == NULL)
+ *((int *) buf) = 0;
+ else
+ {
+ addr = (fqw->source_address & ~15) | (me->qw_pc << 2);
+ *((unsigned_4 *) buf) = H2T_4( addr );
+ }
+
+ return 4;
+}
+
+
/* Read PKE reg into buf in target order */
int
read_pke_reg (struct pke_device *me, int reg_num, void *buf)
pke_code_directhl(me, fw);
else if(IS_PKE_CMD(cmd, UNPACK))
pke_code_unpack(me, fw);
+ else if(cmd == TXVU_VIF_BRK_MASK)
+ {
+ sim_cpu *cpu = STATE_CPU (sd, 0);
+ unsigned_4 pc_addr = (fqw->source_address & ~15) | (me->qw_pc << 2);
+
+ sim_engine_halt (sd, cpu, NULL, pc_addr, sim_stopped, SIM_SIGTRAP);
+ }
/* ... no other commands ... */
else
pke_code_error(me, fw);
int read_pke_reg (struct pke_device *device, int regno, void *buf);
int write_pke_reg (struct pke_device *device, int regno, const void *buf);
int read_pke_pc (struct pke_device *device, void *buf);
+int read_pke_pcx (struct pke_device *device, void *buf);
/* Flags for PKE.flags */