Ignore 'whitebox' attr in flatten with "-wb" option

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 176dc3fc2d5940d8e3e5f885592c4e9f6eafa43b..9e396d6f660e5b29117d1c88eed89ffef710ff3b 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -569,8 +569,8 @@ struct RTLIL::AttrObject
        void set_bool_attribute(RTLIL::IdString id);
        bool get_bool_attribute(RTLIL::IdString id) const;
 
-       bool get_blackbox_attribute() const {
-               return get_bool_attribute("\\blackbox") || get_bool_attribute("\\whitebox");
+       bool get_blackbox_attribute(bool ignore_wb=false) const {
+               return get_bool_attribute("\\blackbox") || (!ignore_wb && get_bool_attribute("\\whitebox"));
        }
 
        void set_strpool_attribute(RTLIL::IdString id, const pool<string> &data);

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index d694e8165e5fc154d186279bc2db23f8f8d2c639..82c815e2edfeebb98a274599e1973f5cd77ab568 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -84,6 +84,7 @@ struct TechmapWorker
        bool flatten_mode;
        bool recursive_mode;
        bool autoproc_mode;
+       bool ignore_wb;
 
        TechmapWorker()
        {
@@ -92,6 +93,7 @@ struct TechmapWorker
                flatten_mode = false;
                recursive_mode = false;
                autoproc_mode = false;
+               ignore_wb = false;
        }
 
        std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose)
@@ -472,7 +474,7 @@ struct TechmapWorker
                                RTLIL::Module *tpl = map->modules_[tpl_name];
                                std::map<RTLIL::IdString, RTLIL::Const> parameters(cell->parameters.begin(), cell->parameters.end());
 
-                               if (tpl->get_blackbox_attribute())
+                               if (tpl->get_blackbox_attribute(ignore_wb))
                                        continue;
 
                                if (!flatten_mode)
@@ -1145,7 +1147,7 @@ struct FlattenPass : public Pass {
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
                log("\n");
-               log("    flatten [selection]\n");
+               log("    flatten [options] [selection]\n");
                log("\n");
                log("This pass flattens the design by replacing cells by their implementation. This\n");
                log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
@@ -1154,17 +1156,29 @@ struct FlattenPass : public Pass {
                log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
                log("flattened by this command.\n");
                log("\n");
+               log("    -wb\n");
+               log("        Ignore the 'whitebox' attribute on cell implementations.\n");
+               log("\n");
        }
        void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
        {
                log_header(design, "Executing FLATTEN pass (flatten design).\n");
                log_push();
 
-               extra_args(args, 1, design);
-
                TechmapWorker worker;
                worker.flatten_mode = true;
 
+               size_t argidx;
+               for (argidx = 1; argidx < args.size(); argidx++) {
+                       if (args[argidx] == "-wb") {
+                               worker.ignore_wb = true;
+                               continue;
+                       }
+                       break;
+               }
+               extra_args(args, argidx, design);
+
+
                std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
                for (auto module : design->modules())
                        celltypeMap[module->name].insert(module->name);
@@ -1209,7 +1223,7 @@ struct FlattenPass : public Pass {
 
                        dict<RTLIL::IdString, RTLIL::Module*> new_modules;
                        for (auto mod : vector<Module*>(design->modules()))
-                               if (used_modules[mod->name] || mod->get_blackbox_attribute()) {
+                               if (used_modules[mod->name] || mod->get_blackbox_attribute(worker.ignore_wb)) {
                                        new_modules[mod->name] = mod;
                                } else {
                                        log("Deleting now unused module %s.\n", log_id(mod));