(no commit message)

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 5db0d7cbfa3388353d8ebbd3ed4bae3918a75e64..6cc6820b3c4cdd9ff8ed6fbd48a7433a05a98238 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -4,6 +4,7 @@ Links:
 
 * <https://bugs.libre-soc.org/show_bug.cgi?id=687>
 * [[svp64]]
+* [[sv/branches]]
 
 Condition Register Fields are only 4 bits wide: this presents some
 interesting conceptual challenges for SVP64, particularly with respect to element