options::ceGuidedInst.set( true );
}
}
+ // if sygus is enabled, set the defaults for sygus
if( options::ceGuidedInst() ){
//counterexample-guided instantiation for sygus
if( !options::cegqiSingleInvMode.wasSetByUser() ){
if( !options::instNoEntail.wasSetByUser() ){
options::instNoEntail.set( false );
}
+ if (!options::cbqiFullEffort.wasSetByUser())
+ {
+ // should use full effort cbqi for single invocation and repair const
+ options::cbqiFullEffort.set(true);
+ }
if (options::sygusRew())
{
options::sygusRewSynth.set(true);
if( !conj->needsRefinement() ){
Trace("cegqi-engine-debug") << "Do conjecture check..." << std::endl;
- std::vector<Node> clems;
- conj->doSingleInvCheck(clems);
- if (!clems.empty())
+ if (conj->isSingleInvocation())
{
- d_last_inst_si = true;
- for (const Node& lem : clems)
+ std::vector<Node> clems;
+ conj->doSingleInvCheck(clems);
+ if (!clems.empty())
{
- Trace("cegqi-lemma")
- << "Cegqi::Lemma : single invocation instantiation : " << lem
+ d_last_inst_si = true;
+ for (const Node& lem : clems)
+ {
+ Trace("cegqi-lemma")
+ << "Cegqi::Lemma : single invocation instantiation : " << lem
+ << std::endl;
+ d_quantEngine->addLemma(lem);
+ }
+ d_statistics.d_cegqi_si_lemmas += clems.size();
+ Trace("cegqi-engine") << " ...try single invocation." << std::endl;
+ }
+ else
+ {
+ // This can happen for non-monotonic instantiation strategies. We
+ // set --cbqi-full to ensure that for most strategies (e.g. BV), we
+ // are using a monotonic strategy.
+ Trace("cegqi-warn")
+ << " ...FAILED to add cbqi instantiation for single invocation!"
<< std::endl;
- d_quantEngine->addLemma(lem);
}
- d_statistics.d_cegqi_si_lemmas += clems.size();
- Trace("cegqi-engine") << " ...try single invocation." << std::endl;
return;
}
regress1/sygus/list-head-x.sy \
regress1/sygus/logiccell_help.sy \
regress1/sygus/max.sy \
+ regress1/sygus/max2-bv.sy \
regress1/sygus/multi-fun-polynomial2.sy \
regress1/sygus/nflat-fwd-3.sy \
regress1/sygus/nflat-fwd.sy \
--- /dev/null
+; EXPECT: unsat
+; COMMAND-LINE: --sygus-out=status
+(set-logic BV)
+
+(synth-fun max2 ((x (BitVec 32))(y (BitVec 32))) (BitVec 32)
+)
+
+(declare-var x (BitVec 32))
+
+(declare-var y (BitVec 32))
+
+(constraint
+(bvuge (max2 x y) x)
+)
+
+(constraint
+(bvuge (max2 x y) y)
+)
+
+(constraint
+(or (= x (max2 x y)) (= y (max2 x y)))
+)
+
+(check-synth)
+
+