(no commit message)

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index bbc3e4620652ab2f87fa37dd0b7fe78c2ae9cbb5..b4618ad1e600fb27889e826d213f2df8697e2470 100644 (file)
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -124,7 +124,7 @@ to a *CR Field* (CR0-CR7) and consequently these operands
 (BF, BFA etc) are only 3-bits.
 
 With SVP64 extending the number of CR *Fields* to 128, the number of
-CR *Registers* extends to 16, in order to hold all 128 CR *Fields*
+32-bit CR *Registers* extends to 16, in order to hold all 128 CR *Fields*
 (8 per CR Register). Then, it gets even more strange, when it comes
 to Vectorisation, which applies to the CR *Field* numbers.  The
 hardware-for-loop for Rc=1 for example starts at CR0 for element 0,