RISC-V: Add zhinx extension supports.

The zhinx extension is a sub-extension in zfinx, corresponding to
zfh extension but use GPRs instead of FPRs.

This patch expanded the zfh insn class define, since zfh and zhinx
use the same opcodes, thanks for Nelson's works.

changelog in V2: Add missing classes of 'zfh' and 'zhinx' in
"riscv_multi_subset_supports_ext".

bfd/ChangeLog:

        * elfxx-riscv.c (riscv_multi_subset_supports): New extensions.
        (riscv_multi_subset_supports_ext): New extensions.

gas/ChangeLog:

        * testsuite/gas/riscv/fp-zhinx-insns.d: New test.
        * testsuite/gas/riscv/fp-zhinx-insns.s: New test.

include/ChangeLog:

        * opcode/riscv.h (enum riscv_insn_class): New INSN classes.

opcodes/ChangeLog:

        * riscv-opc.c: Modify INSN_CLASS.

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 2953dc34b2f15c5b5340057281ab7ed34b7fe1f3..92ad03feea06855d7c6f0ead6bd2ce5a1e34ed6e 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1105,6 +1105,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zqinx", "zdinx",   check_implicit_always},
   {"zdinx", "zfinx",   check_implicit_always},
   {"zfinx", "zicsr",   check_implicit_always},
+  {"zhinx", "zfinx",   check_implicit_always},
+  {"zhinx", "zicsr",   check_implicit_always},
   {"zk", "zkn",                check_implicit_always},
   {"zk", "zkr",                check_implicit_always},
   {"zk", "zkt",                check_implicit_always},
@@ -1187,6 +1189,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zfinx",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zdinx",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zqinx",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
+  {"zhinx",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zbb",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zba",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zbc",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
@@ -2365,12 +2368,17 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
              || riscv_subset_supports (rps, "zqinx"));
     case INSN_CLASS_ZFH:
       return riscv_subset_supports (rps, "zfh");
-    case INSN_CLASS_D_AND_ZFH:
+    case INSN_CLASS_ZFH_OR_ZHINX:
+      return riscv_subset_supports (rps, "zfh")
+        || riscv_subset_supports (rps, "zhinx");
+    case INSN_CLASS_D_AND_ZFH_INX:
       return (riscv_subset_supports (rps, "d")
-             && riscv_subset_supports (rps, "zfh") );
-    case INSN_CLASS_Q_AND_ZFH:
+             && riscv_subset_supports (rps, "zfh"))
+           || riscv_subset_supports (rps, "zhinx");
+    case INSN_CLASS_Q_AND_ZFH_INX:
       return (riscv_subset_supports (rps, "q")
-             && riscv_subset_supports (rps, "zfh"));
+             && riscv_subset_supports (rps, "zfh"))
+           || riscv_subset_supports (rps, "zhinx");
     case INSN_CLASS_ZBA:
       return riscv_subset_supports (rps, "zba");
     case INSN_CLASS_ZBB:
@@ -2509,6 +2517,14 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "v' or `zve64d' or `zve64f' or `zve32f";
     case INSN_CLASS_SVINVAL:
       return "svinval";
+    case INSN_CLASS_ZFH:
+      return "zfh";
+    case INSN_CLASS_ZFH_OR_ZHINX:
+      return "zfh' or 'zhinx";
+    case INSN_CLASS_D_AND_ZFH_INX:
+      return "('d' and 'zfh') or 'zhinx";
+    case INSN_CLASS_Q_AND_ZFH_INX:
+      return "('q' and 'zfh') or 'zhinx";
     default:
       rps->error_handler
         (_("internal: unreachable INSN_CLASS_*"));

diff --git a/gas/testsuite/gas/riscv/fp-zhinx-insns.d b/gas/testsuite/gas/riscv/fp-zhinx-insns.d
new file mode 100644 (file)
index 0000000..6e1c40e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fp-zhinx-insns.d
@@ -0,0 +1,66 @@
+#as: -march=rv64ima_zhinx
+#source: fp-zhinx-insns.s
+#objdump: -dr
+
+.*:[   ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[      ]+[0-9a-f]+:[   ]+24b59553[     ]+fneg.h[       ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+24b5a553[     ]+fabs.h[       ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+24c58553[     ]+fsgnj.h[      ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+24c59553[     ]+fsgnjn.h[     ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+24c5a553[     ]+fsgnjx.h[     ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+04c5f553[     ]+fadd.h[       ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+04c58553[     ]+fadd.h[       ]+a0,a1,a2,rne
+[      ]+[0-9a-f]+:[   ]+0cc5f553[     ]+fsub.h[       ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+0cc58553[     ]+fsub.h[       ]+a0,a1,a2,rne
+[      ]+[0-9a-f]+:[   ]+14c5f553[     ]+fmul.h[       ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+14c58553[     ]+fmul.h[       ]+a0,a1,a2,rne
+[      ]+[0-9a-f]+:[   ]+1cc5f553[     ]+fdiv.h[       ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+1cc58553[     ]+fdiv.h[       ]+a0,a1,a2,rne
+[      ]+[0-9a-f]+:[   ]+5c05f553[     ]+fsqrt.h[      ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+5c058553[     ]+fsqrt.h[      ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+2cc58553[     ]+fmin.h[       ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+2cc59553[     ]+fmax.h[       ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+6cc5f543[     ]+fmadd.h[      ]+a0,a1,a2,a3
+[      ]+[0-9a-f]+:[   ]+6cc58543[     ]+fmadd.h[      ]+a0,a1,a2,a3,rne
+[      ]+[0-9a-f]+:[   ]+6cc5f54f[     ]+fnmadd.h[     ]+a0,a1,a2,a3
+[      ]+[0-9a-f]+:[   ]+6cc5854f[     ]+fnmadd.h[     ]+a0,a1,a2,a3,rne
+[      ]+[0-9a-f]+:[   ]+6cc5f547[     ]+fmsub.h[      ]+a0,a1,a2,a3
+[      ]+[0-9a-f]+:[   ]+6cc58547[     ]+fmsub.h[      ]+a0,a1,a2,a3,rne
+[      ]+[0-9a-f]+:[   ]+6cc5f54b[     ]+fnmsub.h[     ]+a0,a1,a2,a3
+[      ]+[0-9a-f]+:[   ]+6cc5854b[     ]+fnmsub.h[     ]+a0,a1,a2,a3,rne
+[      ]+[0-9a-f]+:[   ]+c405f553[     ]+fcvt.w.h[     ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+c4058553[     ]+fcvt.w.h[     ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+c415f553[     ]+fcvt.wu.h[    ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+c4158553[     ]+fcvt.wu.h[    ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+d405f553[     ]+fcvt.h.w[     ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+d4058553[     ]+fcvt.h.w[     ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+d415f553[     ]+fcvt.h.wu[    ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+d4158553[     ]+fcvt.h.wu[    ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+c425f553[     ]+fcvt.l.h[     ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+c4258553[     ]+fcvt.l.h[     ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+c435f553[     ]+fcvt.lu.h[    ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+c4358553[     ]+fcvt.lu.h[    ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+d425f553[     ]+fcvt.h.l[     ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+d4258553[     ]+fcvt.h.l[     ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+d435f553[     ]+fcvt.h.lu[    ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+d4358553[     ]+fcvt.h.lu[    ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+40258553[     ]+fcvt.s.h[     ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+42258553[     ]+fcvt.d.h[     ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+46258553[     ]+fcvt.q.h[     ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+4405f553[     ]+fcvt.h.s[     ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+44058553[     ]+fcvt.h.s[     ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+4415f553[     ]+fcvt.h.d[     ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+44158553[     ]+fcvt.h.d[     ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+4435f553[     ]+fcvt.h.q[     ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+44358553[     ]+fcvt.h.q[     ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+e4059553[     ]+fclass.h[     ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+a4c5a553[     ]+feq.h[        ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+a4c59553[     ]+flt.h[        ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+a4c58553[     ]+fle.h[        ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+a4c59553[     ]+flt.h[        ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+a4c58553[     ]+fle.h[        ]+a0,a1,a2

diff --git a/gas/testsuite/gas/riscv/fp-zhinx-insns.s b/gas/testsuite/gas/riscv/fp-zhinx-insns.s
new file mode 100644 (file)
index 0000000..75e2d5a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fp-zhinx-insns.s
@@ -0,0 +1,59 @@
+       fneg.h          a0, a1
+       fabs.h          a0, a1
+       fsgnj.h         a0, a1, a2
+       fsgnjn.h        a0, a1, a2
+       fsgnjx.h        a0, a1, a2
+       fadd.h          a0, a1, a2
+       fadd.h          a0, a1, a2, rne
+       fsub.h          a0, a1, a2
+       fsub.h          a0, a1, a2, rne
+       fmul.h          a0, a1, a2
+       fmul.h          a0, a1, a2, rne
+       fdiv.h          a0, a1, a2
+       fdiv.h          a0, a1, a2, rne
+       fsqrt.h         a0, a1
+       fsqrt.h         a0, a1, rne
+       fmin.h          a0, a1, a2
+       fmax.h          a0, a1, a2
+       fmadd.h         a0, a1, a2, a3
+       fmadd.h         a0, a1, a2, a3, rne
+       fnmadd.h        a0, a1, a2, a3
+       fnmadd.h        a0, a1, a2, a3, rne
+       fmsub.h         a0, a1, a2, a3
+       fmsub.h         a0, a1, a2, a3, rne
+       fnmsub.h        a0, a1, a2, a3
+       fnmsub.h        a0, a1, a2, a3, rne
+
+       fcvt.w.h        a0, a1
+       fcvt.w.h        a0, a1, rne
+       fcvt.wu.h       a0, a1
+       fcvt.wu.h       a0, a1, rne
+       fcvt.h.w        a0, a1
+       fcvt.h.w        a0, a1, rne
+       fcvt.h.wu       a0, a1
+       fcvt.h.wu       a0, a1, rne
+       fcvt.l.h        a0, a1
+       fcvt.l.h        a0, a1, rne
+       fcvt.lu.h       a0, a1
+       fcvt.lu.h       a0, a1, rne
+       fcvt.h.l        a0, a1
+       fcvt.h.l        a0, a1, rne
+       fcvt.h.lu       a0, a1
+       fcvt.h.lu       a0, a1, rne
+
+       fcvt.s.h        a0, a1
+       fcvt.d.h        a0, a1
+       fcvt.q.h        a0, a1
+       fcvt.h.s        a0, a1
+       fcvt.h.s        a0, a1, rne
+       fcvt.h.d        a0, a1
+       fcvt.h.d        a0, a1, rne
+       fcvt.h.q        a0, a1
+       fcvt.h.q        a0, a1, rne
+       fclass.h        a0, a1
+
+       feq.h           a0, a1, a2
+       flt.h           a0, a1, a2
+       fle.h           a0, a1, a2
+       fgt.h           a0, a2, a1
+       fge.h           a0, a2, a1

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 0d1fbcf8fc5e10333f05b860f78f0905f6b20ac0..f0beceaec444443fa92a40d41f1b9465c66c6f2c 100644 (file)
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -371,8 +371,9 @@ enum riscv_insn_class
   INSN_CLASS_D_OR_ZDINX,
   INSN_CLASS_Q_OR_ZQINX,
   INSN_CLASS_ZFH,
-  INSN_CLASS_D_AND_ZFH,
-  INSN_CLASS_Q_AND_ZFH,
+  INSN_CLASS_ZFH_OR_ZHINX,
+  INSN_CLASS_D_AND_ZFH_INX,
+  INSN_CLASS_Q_AND_ZFH_INX,
   INSN_CLASS_ZBA,
   INSN_CLASS_ZBB,
   INSN_CLASS_ZBC,

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index bbd4a3718f64ee21e886a53933dddbc4bdaccdd0..6355f8059f5d7ece1cd75b4e9799defb0c7479fd 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -578,64 +578,64 @@ const struct riscv_opcode riscv_opcodes[] =
 {"fsh",        0, INSN_CLASS_ZFH,  "T,q(s)",    MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE },
 {"fsh",        0, INSN_CLASS_ZFH,  "T,A,s",     0, (int) M_FSH, match_never, INSN_MACRO },
 {"fmv.h",      0, INSN_CLASS_ZFH,  "D,U",       MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS },
-{"fneg.h",     0, INSN_CLASS_ZFH,  "D,U",       MATCH_FSGNJN_H, MASK_FSGNJN_H, match_rs1_eq_rs2, INSN_ALIAS },
-{"fabs.h",     0, INSN_CLASS_ZFH,  "D,U",       MATCH_FSGNJX_H, MASK_FSGNJX_H, match_rs1_eq_rs2, INSN_ALIAS },
-{"fsgnj.h",    0, INSN_CLASS_ZFH,  "D,S,T",     MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 },
-{"fsgnjn.h",   0, INSN_CLASS_ZFH,  "D,S,T",     MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 },
-{"fsgnjx.h",   0, INSN_CLASS_ZFH,  "D,S,T",     MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 },
-{"fadd.h",     0, INSN_CLASS_ZFH,  "D,S,T",     MATCH_FADD_H|MASK_RM, MASK_FADD_H|MASK_RM, match_opcode, 0 },
-{"fadd.h",     0, INSN_CLASS_ZFH,  "D,S,T,m",   MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 },
-{"fsub.h",     0, INSN_CLASS_ZFH,  "D,S,T",     MATCH_FSUB_H|MASK_RM, MASK_FSUB_H|MASK_RM, match_opcode, 0 },
-{"fsub.h",     0, INSN_CLASS_ZFH,  "D,S,T,m",   MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 },
-{"fmul.h",     0, INSN_CLASS_ZFH,  "D,S,T",     MATCH_FMUL_H|MASK_RM, MASK_FMUL_H|MASK_RM, match_opcode, 0 },
-{"fmul.h",     0, INSN_CLASS_ZFH,  "D,S,T,m",   MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 },
-{"fdiv.h",     0, INSN_CLASS_ZFH,  "D,S,T",     MATCH_FDIV_H|MASK_RM, MASK_FDIV_H|MASK_RM, match_opcode, 0 },
-{"fdiv.h",     0, INSN_CLASS_ZFH,  "D,S,T,m",   MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 },
-{"fsqrt.h",    0, INSN_CLASS_ZFH,  "D,S",       MATCH_FSQRT_H|MASK_RM, MASK_FSQRT_H|MASK_RM, match_opcode, 0 },
-{"fsqrt.h",    0, INSN_CLASS_ZFH,  "D,S,m",     MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 },
-{"fmin.h",     0, INSN_CLASS_ZFH,  "D,S,T",     MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 },
-{"fmax.h",     0, INSN_CLASS_ZFH,  "D,S,T",     MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 },
-{"fmadd.h",    0, INSN_CLASS_ZFH,  "D,S,T,R",   MATCH_FMADD_H|MASK_RM, MASK_FMADD_H|MASK_RM, match_opcode, 0 },
-{"fmadd.h",    0, INSN_CLASS_ZFH,  "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 },
-{"fnmadd.h",   0, INSN_CLASS_ZFH,  "D,S,T,R",   MATCH_FNMADD_H|MASK_RM, MASK_FNMADD_H|MASK_RM, match_opcode, 0 },
-{"fnmadd.h",   0, INSN_CLASS_ZFH,  "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 },
-{"fmsub.h",    0, INSN_CLASS_ZFH,  "D,S,T,R",   MATCH_FMSUB_H|MASK_RM, MASK_FMSUB_H|MASK_RM, match_opcode, 0 },
-{"fmsub.h",    0, INSN_CLASS_ZFH,  "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 },
-{"fnmsub.h",   0, INSN_CLASS_ZFH,  "D,S,T,R",   MATCH_FNMSUB_H|MASK_RM, MASK_FNMSUB_H|MASK_RM, match_opcode, 0 },
-{"fnmsub.h",   0, INSN_CLASS_ZFH,  "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 },
-{"fcvt.w.h",   0, INSN_CLASS_ZFH,  "d,S",       MATCH_FCVT_W_H|MASK_RM, MASK_FCVT_W_H|MASK_RM, match_opcode, 0 },
-{"fcvt.w.h",   0, INSN_CLASS_ZFH,  "d,S,m",     MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 },
-{"fcvt.wu.h",  0, INSN_CLASS_ZFH,  "d,S",       MATCH_FCVT_WU_H|MASK_RM, MASK_FCVT_WU_H|MASK_RM, match_opcode, 0 },
-{"fcvt.wu.h",  0, INSN_CLASS_ZFH,  "d,S,m",     MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 },
-{"fcvt.h.w",   0, INSN_CLASS_ZFH,  "D,s",       MATCH_FCVT_H_W|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 },
-{"fcvt.h.w",   0, INSN_CLASS_ZFH,  "D,s,m",     MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
-{"fcvt.h.wu",  0, INSN_CLASS_ZFH,  "D,s",       MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 },
-{"fcvt.h.wu",  0, INSN_CLASS_ZFH,  "D,s,m",     MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
-{"fcvt.s.h",   0, INSN_CLASS_ZFH,  "D,S",       MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
-{"fcvt.d.h",   0, INSN_CLASS_D_AND_ZFH,  "D,S",       MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 },
-{"fcvt.q.h",   0, INSN_CLASS_Q_AND_ZFH,  "D,S",       MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 },
-{"fcvt.h.s",   0, INSN_CLASS_ZFH,  "D,S",       MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 },
-{"fcvt.h.s",   0, INSN_CLASS_ZFH,  "D,S,m",     MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
-{"fcvt.h.d",   0, INSN_CLASS_D_AND_ZFH,  "D,S",       MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 },
-{"fcvt.h.d",   0, INSN_CLASS_D_AND_ZFH,  "D,S,m",     MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 },
-{"fcvt.h.q",   0, INSN_CLASS_Q_AND_ZFH,  "D,S",       MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.h.q",   0, INSN_CLASS_Q_AND_ZFH,  "D,S,m",     MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
-{"fclass.h",   0, INSN_CLASS_ZFH,  "d,S",       MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
-{"feq.h",      0, INSN_CLASS_ZFH,  "d,S,T",     MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
-{"flt.h",      0, INSN_CLASS_ZFH,  "d,S,T",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
-{"fle.h",      0, INSN_CLASS_ZFH,  "d,S,T",     MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
-{"fgt.h",      0, INSN_CLASS_ZFH,  "d,T,S",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
-{"fge.h",      0, INSN_CLASS_ZFH,  "d,T,S",     MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
+{"fneg.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,U",       MATCH_FSGNJN_H, MASK_FSGNJN_H, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,U",       MATCH_FSGNJX_H, MASK_FSGNJX_H, match_rs1_eq_rs2, INSN_ALIAS },
+{"fsgnj.h",    0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T",     MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 },
+{"fsgnjn.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T",     MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 },
+{"fsgnjx.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T",     MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 },
+{"fadd.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T",     MATCH_FADD_H|MASK_RM, MASK_FADD_H|MASK_RM, match_opcode, 0 },
+{"fadd.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,m",   MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 },
+{"fsub.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T",     MATCH_FSUB_H|MASK_RM, MASK_FSUB_H|MASK_RM, match_opcode, 0 },
+{"fsub.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,m",   MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 },
+{"fmul.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T",     MATCH_FMUL_H|MASK_RM, MASK_FMUL_H|MASK_RM, match_opcode, 0 },
+{"fmul.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,m",   MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 },
+{"fdiv.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T",     MATCH_FDIV_H|MASK_RM, MASK_FDIV_H|MASK_RM, match_opcode, 0 },
+{"fdiv.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,m",   MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 },
+{"fsqrt.h",    0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S",       MATCH_FSQRT_H|MASK_RM, MASK_FSQRT_H|MASK_RM, match_opcode, 0 },
+{"fsqrt.h",    0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,m",     MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 },
+{"fmin.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T",     MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 },
+{"fmax.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T",     MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 },
+{"fmadd.h",    0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,R",   MATCH_FMADD_H|MASK_RM, MASK_FMADD_H|MASK_RM, match_opcode, 0 },
+{"fmadd.h",    0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 },
+{"fnmadd.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,R",   MATCH_FNMADD_H|MASK_RM, MASK_FNMADD_H|MASK_RM, match_opcode, 0 },
+{"fnmadd.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 },
+{"fmsub.h",    0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,R",   MATCH_FMSUB_H|MASK_RM, MASK_FMSUB_H|MASK_RM, match_opcode, 0 },
+{"fmsub.h",    0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 },
+{"fnmsub.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,R",   MATCH_FNMSUB_H|MASK_RM, MASK_FNMSUB_H|MASK_RM, match_opcode, 0 },
+{"fnmsub.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 },
+{"fcvt.w.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "d,S",       MATCH_FCVT_W_H|MASK_RM, MASK_FCVT_W_H|MASK_RM, match_opcode, 0 },
+{"fcvt.w.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "d,S,m",     MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 },
+{"fcvt.wu.h",  0, INSN_CLASS_ZFH_OR_ZHINX,  "d,S",       MATCH_FCVT_WU_H|MASK_RM, MASK_FCVT_WU_H|MASK_RM, match_opcode, 0 },
+{"fcvt.wu.h",  0, INSN_CLASS_ZFH_OR_ZHINX,  "d,S,m",     MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 },
+{"fcvt.h.w",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,s",       MATCH_FCVT_H_W|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 },
+{"fcvt.h.w",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,s,m",     MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
+{"fcvt.h.wu",  0, INSN_CLASS_ZFH_OR_ZHINX,  "D,s",       MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 },
+{"fcvt.h.wu",  0, INSN_CLASS_ZFH_OR_ZHINX,  "D,s,m",     MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
+{"fcvt.s.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S",       MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
+{"fcvt.d.h",   0, INSN_CLASS_D_AND_ZFH_INX,  "D,S",       MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 },
+{"fcvt.q.h",   0, INSN_CLASS_Q_AND_ZFH_INX,  "D,S",       MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 },
+{"fcvt.h.s",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S",       MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 },
+{"fcvt.h.s",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,m",     MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
+{"fcvt.h.d",   0, INSN_CLASS_D_AND_ZFH_INX,  "D,S",       MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 },
+{"fcvt.h.d",   0, INSN_CLASS_D_AND_ZFH_INX,  "D,S,m",     MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 },
+{"fcvt.h.q",   0, INSN_CLASS_Q_AND_ZFH_INX,  "D,S",       MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, 0 },
+{"fcvt.h.q",   0, INSN_CLASS_Q_AND_ZFH_INX,  "D,S,m",     MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
+{"fclass.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "d,S",       MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
+{"feq.h",      0, INSN_CLASS_ZFH_OR_ZHINX,  "d,S,T",     MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
+{"flt.h",      0, INSN_CLASS_ZFH_OR_ZHINX,  "d,S,T",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
+{"fle.h",      0, INSN_CLASS_ZFH_OR_ZHINX,  "d,S,T",     MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
+{"fgt.h",      0, INSN_CLASS_ZFH_OR_ZHINX,  "d,T,S",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
+{"fge.h",      0, INSN_CLASS_ZFH_OR_ZHINX,  "d,T,S",     MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
 {"fmv.x.h",    0, INSN_CLASS_ZFH,  "d,S",       MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 },
 {"fmv.h.x",    0, INSN_CLASS_ZFH,  "D,s",       MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 },
-{"fcvt.l.h",  64, INSN_CLASS_ZFH,  "d,S",       MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 },
-{"fcvt.l.h",  64, INSN_CLASS_ZFH,  "d,S,m",     MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 },
-{"fcvt.lu.h", 64, INSN_CLASS_ZFH,  "d,S",       MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 },
-{"fcvt.lu.h", 64, INSN_CLASS_ZFH,  "d,S,m",     MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 },
-{"fcvt.h.l",  64, INSN_CLASS_ZFH,  "D,s",       MATCH_FCVT_H_L|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
-{"fcvt.h.l",  64, INSN_CLASS_ZFH,  "D,s,m",     MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 },
-{"fcvt.h.lu", 64, INSN_CLASS_ZFH,  "D,s",       MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
-{"fcvt.h.lu", 64, INSN_CLASS_ZFH,  "D,s,m",     MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
+{"fcvt.l.h",  64, INSN_CLASS_ZFH_OR_ZHINX,  "d,S",       MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 },
+{"fcvt.l.h",  64, INSN_CLASS_ZFH_OR_ZHINX,  "d,S,m",     MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 },
+{"fcvt.lu.h", 64, INSN_CLASS_ZFH_OR_ZHINX,  "d,S",       MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 },
+{"fcvt.lu.h", 64, INSN_CLASS_ZFH_OR_ZHINX,  "d,S,m",     MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 },
+{"fcvt.h.l",  64, INSN_CLASS_ZFH_OR_ZHINX,  "D,s",       MATCH_FCVT_H_L|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
+{"fcvt.h.l",  64, INSN_CLASS_ZFH_OR_ZHINX,  "D,s,m",     MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 },
+{"fcvt.h.lu", 64, INSN_CLASS_ZFH_OR_ZHINX,  "D,s",       MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
+{"fcvt.h.lu", 64, INSN_CLASS_ZFH_OR_ZHINX,  "D,s,m",     MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
 
 /* Single-precision floating-point instruction subset.  */
 {"frcsr",      0, INSN_CLASS_F_OR_ZFINX,   "d",         MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },