i965: Set MaxCombinedUniformBlocks properly.

Up until now, we've been letting core Mesa initialize it to 36 for us
(which is presumably BRW_MAX_UBO (12) * (VS+GS+FS stages -> 3)).

With compute and tessellation, we need to increase this.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index e70ad982f482cf339f75eb11b027f72210f5909f..2ea0a9eca923f620b7aab5426239b62828eeff32 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -391,6 +391,7 @@ brw_initialize_context_constants(struct brw_context *brw)
            ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits);
 
    ctx->Const.MaxUniformBufferBindings = num_stages * BRW_MAX_UBO;
+   ctx->Const.MaxCombinedUniformBlocks = num_stages * BRW_MAX_UBO;
    ctx->Const.MaxCombinedAtomicBuffers = num_stages * BRW_MAX_ABO;
    ctx->Const.MaxCombinedShaderStorageBlocks = num_stages * BRW_MAX_SSBO;
    ctx->Const.MaxShaderStorageBufferBindings = num_stages * BRW_MAX_SSBO;