if (unlikely(pc == PC_SERIALIZE)) { \
pc = state.pc; \
state.serialized = true; \
- continue; \
+ break; \
}
try
}
catch(trap_t& t)
{
- state.pc = take_trap(t, pc);
+ take_trap(t, pc);
}
update_timer(&state, instret);
set_csr(CSR_MSTATUS, s);
}
-reg_t processor_t::take_trap(trap_t& t, reg_t epc)
+void processor_t::take_trap(trap_t& t, reg_t epc)
{
if (debug)
fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
id, t.name(), epc);
- reg_t tvec = DEFAULT_MTVEC + 0x40 * get_field(state.mstatus, MSTATUS_PRV);
+ state.pc = DEFAULT_MTVEC + 0x40 * get_field(state.mstatus, MSTATUS_PRV);
push_privilege_stack();
yield_load_reservation();
state.mcause = t.cause();
state.mepc = epc;
t.side_effects(&state); // might set badvaddr etc.
- return tvec;
}
void processor_t::deliver_ipi()
std::map<size_t,size_t> pc_histogram;
void take_interrupt(); // take a trap if any interrupts are pending
- reg_t take_trap(trap_t& t, reg_t epc); // take an exception
+ void take_trap(trap_t& t, reg_t epc); // take an exception
void disasm(insn_t insn); // disassemble and print an instruction
friend class sim_t;