from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.fsm import FSM, NextState
-from lib.sata.k7sataphy.std import *
+from lib.sata.std import *
from lib.sata.k7sataphy.gtx import GTXE2_COMMON
class K7SATAPHYCRG(Module):
p_BANDWIDTH="HIGH", p_COMPENSATION="ZHOLD", i_RST=mmcm_reset, o_LOCKED=mmcm_locked,
# DRP
- i_DCLK=0, i_DEN=0, i_DWE=0, #o_DRDY=,
+ i_DCLK=0, i_DEN=0, i_DWE=0, #o_DRDY=,
i_DADDR=0, i_DI=0, #o_DO=,
# VCO
from migen.genlib.fsm import FSM, NextState
from migen.flow.actor import Sink, Source
-from lib.sata.k7sataphy.std import *
+from lib.sata.std import *
def us(t, clk_freq):
clk_period_us = 1000000/clk_freq
)
fsm.act("SEND_ALIGN",
gtx.txelecidle.eq(0),
- self.source.data.eq(ALIGN_VAL),
+ self.source.data.eq(primitives["ALIGN"]),
self.source.charisk.eq(0b0001),
If(non_align_cnt == 3,
NextState("READY")
)
fsm.act("READY",
gtx.txelecidle.eq(0),
- self.source.data.eq(SYNC_VAL),
+ self.source.data.eq(primitives["SYNC"]),
self.source.charisk.eq(0b0001),
self.ready.eq(1),
)
gtx.txcomwake.eq(txcomwake & ~txcomwake_d),
]
- self.comb += align_detect.eq(self.sink.stb & (self.sink.data == ALIGN_VAL));
+ self.comb += align_detect.eq(self.sink.stb & (self.sink.data == primitives["ALIGN"]));
self.sync += \
If(fsm.ongoing("RESET"),
align_timeout_cnt.eq(us(873, clk_freq))
fsm.act("SEND_ALIGN",
gtx.txelecidle.eq(0),
gtx.rxalign.eq(1),
- self.source.data.eq(ALIGN_VAL),
+ self.source.data.eq(primitives["ALIGN"]),
self.source.charisk.eq(0b0001),
If(align_detect,
NextState("READY")
gtx.txcomwake.eq(txcomwake & ~txcomwake_d),
]
- self.comb += align_detect.eq(self.sink.stb & (self.sink.data == ALIGN_VAL));
+ self.comb += align_detect.eq(self.sink.stb & (self.sink.data == primitives["ALIGN"]));
self.sync += \
If(fsm.ongoing("RESET"),
align_timeout_cnt.eq(us(55, clk_freq))
from migen.actorlib.fifo import AsyncFIFO
from migen.flow.actor import Sink, Source
-from lib.sata.k7sataphy.std import *
+from lib.sata.std import *
class K7SATAPHYDatapathRX(Module):
def __init__(self):
If(ctrl.ready,
If(send_align,
tx.sink.stb.eq(1),
- tx.sink.data.eq(ALIGN_VAL),
+ tx.sink.data.eq(primitives["ALIGN"]),
tx.sink.charisk.eq(0b0001),
self.sink.ack.eq(0)
).Else(
from migen.fhdl.std import *
from migen.genlib.cdc import *
-from lib.sata.k7sataphy.std import *
+from lib.sata.std import *
class _PulseSynchronizer(PulseSynchronizer):
def __init__(self, i, idomain, o, odomain):
+++ /dev/null
-from migen.fhdl.std import *
-from migen.genlib.record import *
-
-ALIGN_VAL = 0x7B4A4ABC
-SYNC_VAL = 0xB5B5957C
-
-def ones(width):
- return 2**width-1
from migen.fhdl.std import *
+from migen.genlib.record import *
-ALIGN_VAL = 0x7B4A4ABC
-SYNC_VAL = 0xB5B5957C
-R_RDY_VAL = 0x4A4A957C
-R_OK_VAL = 0x3535B57C
-R_ERR_VAL = 0x5656B57C
-R_IP_VAL = 0X5555B57C
-X_RDY_VAL = 0x5757B57C
-CONT_VAL = 0x9999AA7C
-WTRM_VAL = 0x5858B57C
-SOF_VAL = 0x3737B57C
-EOF_VAL = 0xD5D5B57C
-HOLD_VAL = 0xD5D5AA7C
-HOLD_ACK = 0X9595AA7C
+primitives = {
+ "ALIGN" : 0x7B4A4ABC,
+ "SYNC" : 0xB5B5957C,
+ "R_RDY" : 0x4A4A957C,
+ "R_OK" : 0x3535B57C,
+ "R_ERR" : 0x5656B57C,
+ "R_IP" : 0X5555B57C,
+ "X_RDY" : 0x5757B57C,
+ "CONT" : 0x9999AA7C,
+ "WTRM" : 0x5858B57C,
+ "SOF" : 0x3737B57C,
+ "EOF" : 0xD5D5B57C,
+ "HOLD" : 0xD5D5AA7C,
+ "HOLD" : 0X9595AA7C
+}
+
+def ones(width):
+ return 2**width-1
def phy_layout(dw):
layout = [