r600g: rename radeon_ws_bo to r600_bo
authorJerome Glisse <jglisse@redhat.com>
Mon, 4 Oct 2010 14:06:13 +0000 (10:06 -0400)
committerJerome Glisse <jglisse@redhat.com>
Mon, 4 Oct 2010 21:25:19 +0000 (17:25 -0400)
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
12 files changed:
src/gallium/drivers/r600/evergreen_state.c
src/gallium/drivers/r600/r600.h
src/gallium/drivers/r600/r600_buffer.c
src/gallium/drivers/r600/r600_pipe.h
src/gallium/drivers/r600/r600_resource.h
src/gallium/drivers/r600/r600_shader.c
src/gallium/drivers/r600/r600_state.c
src/gallium/drivers/r600/r600_texture.c
src/gallium/winsys/r600/drm/evergreen_hw_context.c
src/gallium/winsys/r600/drm/r600_hw_context.c
src/gallium/winsys/r600/drm/r600_priv.h
src/gallium/winsys/r600/drm/radeon_ws_bo.c

index 70799f6378ed65a69e2ac02c3b6e30078a55a024..6fcb2ae6f322b18a9f1456eff5be46e03af101c1 100644 (file)
@@ -406,7 +406,7 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
        unsigned format;
        uint32_t word4 = 0, yuv_format = 0, pitch = 0;
        unsigned char swizzle[4];
-       struct radeon_ws_bo *bo[2];
+       struct r600_bo *bo[2];
 
        if (resource == NULL)
                return NULL;
@@ -539,7 +539,7 @@ static void evergreen_delete_state(struct pipe_context *ctx, void *state)
                rctx->states[rstate->id] = NULL;
        }
        for (int i = 0; i < rstate->nregs; i++) {
-               radeon_ws_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
+               r600_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
        }
        free(rstate);
 }
@@ -738,7 +738,7 @@ static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state
        unsigned color_info;
        unsigned format, swap, ntype;
        const struct util_format_description *desc;
-       struct radeon_ws_bo *bo[3];
+       struct r600_bo *bo[3];
 
        rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
        rbuffer = &rtex->resource;
index f0b74ad8740b59ba34b86465ebbb4691e37009f4..dd3c4e3006524ad63176be47c7db47324324aee4 100644 (file)
@@ -103,15 +103,15 @@ enum radeon_family r600_get_family(struct radeon *rw);
 enum chip_class r600_get_family_class(struct radeon *radeon);
 
 /* lowlevel WS bo */
-struct radeon_ws_bo;
-struct radeon_ws_bo *radeon_ws_bo(struct radeon *radeon,
+struct r600_bo;
+struct r600_bo *r600_bo(struct radeon *radeon,
                                  unsigned size, unsigned alignment, unsigned usage);
-struct radeon_ws_bo *radeon_ws_bo_handle(struct radeon *radeon,
+struct r600_bo *r600_bo_handle(struct radeon *radeon,
                                         unsigned handle);
-void *radeon_ws_bo_map(struct radeon *radeon, struct radeon_ws_bo *bo, unsigned usage, void *ctx);
-void radeon_ws_bo_unmap(struct radeon *radeon, struct radeon_ws_bo *bo);
-void radeon_ws_bo_reference(struct radeon *radeon, struct radeon_ws_bo **dst,
-                           struct radeon_ws_bo *src);
+void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx);
+void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo);
+void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst,
+                           struct r600_bo *src);
 
 /* R600/R700 STATES */
 #define R600_GROUP_MAX                 16
@@ -122,7 +122,7 @@ struct r600_pipe_reg {
        u32                             offset;
        u32                             mask;
        u32                             value;
-       struct radeon_ws_bo             *bo;
+       struct r600_bo          *bo;
 };
 
 struct r600_pipe_state {
@@ -133,7 +133,7 @@ struct r600_pipe_state {
 
 static inline void r600_pipe_state_add_reg(struct r600_pipe_state *state,
                                        u32 offset, u32 value, u32 mask,
-                                       struct radeon_ws_bo *bo)
+                                       struct r600_bo *bo)
 {
        state->regs[state->nregs].offset = offset;
        state->regs[state->nregs].value = value;
@@ -147,7 +147,7 @@ static inline void r600_pipe_state_add_reg(struct r600_pipe_state *state,
 #define R600_BLOCK_STATUS_DIRTY                (1 << 1)
 
 struct r600_block_reloc {
-       struct radeon_ws_bo     *bo;
+       struct r600_bo  *bo;
        unsigned                nreloc;
        unsigned                bo_pm4_index[R600_BLOCK_MAX_BO];
 };
@@ -195,7 +195,7 @@ struct r600_query {
        /* if we've flushed the query */
        unsigned                                state;
        /* The buffer where query results are stored. */
-       struct radeon_ws_bo                     *buffer;
+       struct r600_bo                  *buffer;
        unsigned                                buffer_size;
        /* linked list of queries */
        struct list_head                        list;
@@ -232,7 +232,7 @@ struct r600_draw {
        u32                     vgt_index_type;
        u32                     vgt_draw_initiator;
        u32                     indices_bo_offset;
-       struct radeon_ws_bo     *indices;
+       struct r600_bo          *indices;
 };
 
 int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
index 1bbcb310ebfdaa5d2e9eb271c2789d69f01ec388..2bfa4e22fecff34ecc8e08fcc974d03d3af6eefe 100644 (file)
@@ -69,7 +69,7 @@ struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
                                         const struct pipe_resource *templ)
 {
        struct r600_resource_buffer *rbuffer;
-       struct radeon_ws_bo *bo;
+       struct r600_bo *bo;
        /* XXX We probably want a different alignment for buffers and textures. */
        unsigned alignment = 4096;
 
@@ -86,7 +86,7 @@ struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
        rbuffer->r.base.vtbl = &r600_buffer_vtbl;
        rbuffer->r.size = rbuffer->r.base.b.width0;
        rbuffer->r.domain = r600_domain_from_usage(rbuffer->r.base.b.bind);
-       bo = radeon_ws_bo((struct radeon*)screen->winsys, rbuffer->r.base.b.width0, alignment, rbuffer->r.base.b.bind);
+       bo = r600_bo((struct radeon*)screen->winsys, rbuffer->r.base.b.width0, alignment, rbuffer->r.base.b.bind);
        if (bo == NULL) {
                FREE(rbuffer);
                return NULL;
@@ -129,7 +129,7 @@ static void r600_buffer_destroy(struct pipe_screen *screen,
        struct r600_resource_buffer *rbuffer = r600_buffer(buf);
 
        if (rbuffer->r.bo) {
-               radeon_ws_bo_reference((struct radeon*)screen->winsys, &rbuffer->r.bo, NULL);
+               r600_bo_reference((struct radeon*)screen->winsys, &rbuffer->r.bo, NULL);
        }
        FREE(rbuffer);
 }
@@ -153,9 +153,9 @@ static void *r600_buffer_transfer_map(struct pipe_context *pipe,
                                flush = TRUE;
                        
                        if (flush) {
-                               radeon_ws_bo_reference((struct radeon*)pipe->winsys, &rbuffer->r.bo, NULL);
+                               r600_bo_reference((struct radeon*)pipe->winsys, &rbuffer->r.bo, NULL);
                                rbuffer->num_ranges = 0;
-                               rbuffer->r.bo = radeon_ws_bo((struct radeon*)pipe->winsys,
+                               rbuffer->r.bo = r600_bo((struct radeon*)pipe->winsys,
                                                             rbuffer->r.base.b.width0, 0,
                                                             rbuffer->r.base.b.bind);
                                break;
@@ -168,7 +168,7 @@ static void *r600_buffer_transfer_map(struct pipe_context *pipe,
        if (transfer->usage & PIPE_TRANSFER_WRITE) {
                write = 1;
        }
-       data = radeon_ws_bo_map((struct radeon*)pipe->winsys, rbuffer->r.bo, transfer->usage, pipe);
+       data = r600_bo_map((struct radeon*)pipe->winsys, rbuffer->r.bo, transfer->usage, pipe);
        if (!data)
                return NULL;
 
@@ -181,7 +181,7 @@ static void r600_buffer_transfer_unmap(struct pipe_context *pipe,
        struct r600_resource_buffer *rbuffer = r600_buffer(transfer->resource);
 
        if (rbuffer->r.bo)
-               radeon_ws_bo_unmap((struct radeon*)pipe->winsys, rbuffer->r.bo);
+               r600_bo_unmap((struct radeon*)pipe->winsys, rbuffer->r.bo);
 }
 
 static void r600_buffer_transfer_flush_region(struct pipe_context *pipe,
@@ -225,16 +225,16 @@ struct pipe_resource *r600_buffer_from_handle(struct pipe_screen *screen,
 {
        struct radeon *rw = (struct radeon*)screen->winsys;
        struct r600_resource *rbuffer;
-       struct radeon_ws_bo *bo = NULL;
+       struct r600_bo *bo = NULL;
 
-       bo = radeon_ws_bo_handle(rw, whandle->handle);
+       bo = r600_bo_handle(rw, whandle->handle);
        if (bo == NULL) {
                return NULL;
        }
 
        rbuffer = CALLOC_STRUCT(r600_resource);
        if (rbuffer == NULL) {
-               radeon_ws_bo_reference(rw, &bo, NULL);
+               r600_bo_reference(rw, &bo, NULL);
                return NULL;
        }
 
index 18ebb0eb22697e97f751bb46653fbee32f133d3a..c46029a5617196fa885a4ed5ec736f6e1cc9e09d 100644 (file)
@@ -88,7 +88,7 @@ struct r600_vertex_element
 struct r600_pipe_shader {
        struct r600_shader              shader;
        struct r600_pipe_state          rstate;
-       struct radeon_ws_bo             *bo;
+       struct r600_bo                  *bo;
        struct r600_vertex_element      vertex_elements;
 };
 
index ae1ad24bfd550ad04f64f99f88702251e3f76bac..f6377ea802b9ccea1e6c470fe5a572c1cb51c59f 100644 (file)
@@ -41,7 +41,7 @@ struct r600_transfer {
  */
 struct r600_resource {
        struct u_resource               base;
-       struct radeon_ws_bo             *bo;
+       struct r600_bo                  *bo;
        u32                             domain;
        u32                             flink;
        u32                             size;
index 21b9180582408abb88f0bf6116c09d6dc4c0bdd5..e9d4ee13b94e584e1f1e261ea5c21454d5df1869 100644 (file)
@@ -200,13 +200,13 @@ static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *s
 
        /* copy new shader */
        if (shader->bo == NULL) {
-               shader->bo = radeon_ws_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
+               shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
                if (shader->bo == NULL) {
                        return -ENOMEM;
                }
-               ptr = radeon_ws_bo_map(rctx->radeon, shader->bo, 0, NULL);
+               ptr = r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
                memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
-               radeon_ws_bo_unmap(rctx->radeon, shader->bo);
+               r600_bo_unmap(rctx->radeon, shader->bo);
        }
        /* build state */
        rshader->flat_shade = rctx->flatshade;
@@ -254,7 +254,7 @@ static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader
        for (i = 0; i < rctx->vertex_elements->count; i++) {
                resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
        }
-       radeon_ws_bo_reference(rctx->radeon, &rshader->bo, NULL);
+       r600_bo_reference(rctx->radeon, &rshader->bo, NULL);
        LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
                switch (cf->inst) {
                case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
index 2814ecc239a8835c423043ca42192478728a3ff4..326e3aa1419404acca1f1585210f592580f45fd9 100644 (file)
@@ -606,7 +606,7 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
        unsigned format;
        uint32_t word4 = 0, yuv_format = 0, pitch = 0;
        unsigned char swizzle[4], array_mode = 0, tile_type = 0;
-       struct radeon_ws_bo *bo[2];
+       struct r600_bo *bo[2];
 
        if (resource == NULL)
                return NULL;
@@ -739,7 +739,7 @@ static void r600_delete_state(struct pipe_context *ctx, void *state)
                rctx->states[rstate->id] = NULL;
        }
        for (int i = 0; i < rstate->nregs; i++) {
-               radeon_ws_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
+               r600_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
        }
        free(rstate);
 }
@@ -940,7 +940,7 @@ static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta
        unsigned color_info;
        unsigned format, swap, ntype;
        const struct util_format_description *desc;
-       struct radeon_ws_bo *bo[3];
+       struct r600_bo *bo[3];
 
        rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
        rbuffer = &rtex->resource;
index f03d6fcfd60573c984dcf5aea1acef416dd0cab4..c46bfa66ba1a9ab85a2d3791fe3ece349efcc506 100644 (file)
@@ -127,7 +127,7 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
        /* FIXME alignment 4096 enought ? too much ? */
        resource->domain = r600_domain_from_usage(resource->base.b.bind);
        resource->size = rtex->size;
-       resource->bo = radeon_ws_bo(radeon, rtex->size, 4096, 0);
+       resource->bo = r600_bo(radeon, rtex->size, 4096, 0);
        if (resource->bo == NULL) {
                FREE(rtex);
                return NULL;
@@ -146,7 +146,7 @@ static void r600_texture_destroy(struct pipe_screen *screen,
                pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 
        if (resource->bo) {
-               radeon_ws_bo_reference(radeon, &resource->bo, NULL);
+               r600_bo_reference(radeon, &resource->bo, NULL);
        }
        FREE(rtex);
 }
@@ -190,7 +190,7 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
        struct radeon *rw = (struct radeon*)screen->winsys;
        struct r600_resource_texture *rtex;
        struct r600_resource *resource;
-       struct radeon_ws_bo *bo = NULL;
+       struct r600_bo *bo = NULL;
 
        /* Support only 2D textures without mipmaps */
        if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
@@ -201,7 +201,7 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
        if (rtex == NULL)
                return NULL;
 
-       bo = radeon_ws_bo_handle(rw, whandle->handle);
+       bo = r600_bo_handle(rw, whandle->handle);
        if (bo == NULL) {
                FREE(rtex);
                return NULL;
@@ -359,7 +359,7 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
                                struct pipe_transfer* transfer)
 {
        struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
-       struct radeon_ws_bo *bo;
+       struct r600_bo *bo;
        enum pipe_format format = transfer->resource->format;
        struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
        unsigned long offset = 0;
@@ -379,7 +379,7 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
                        transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
                        transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
        }
-       map = radeon_ws_bo_map(radeon, bo, 0, ctx);
+       map = r600_bo_map(radeon, bo, 0, ctx);
        if (!map) {
                return NULL;
        }
@@ -392,7 +392,7 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
 {
        struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
        struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
-       struct radeon_ws_bo *bo;
+       struct r600_bo *bo;
 
        if (rtransfer->linear_texture) {
                bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
@@ -405,7 +405,7 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
                        bo = ((struct r600_resource *)transfer->resource)->bo;
                }
        }
-       radeon_ws_bo_unmap(radeon, bo);
+       r600_bo_unmap(radeon, bo);
 }
 
 struct u_resource_vtbl r600_texture_vtbl =
index c3569e60e881a8d7502258f21c04ab7a12444711..fadfe2869214fe704e29508f3dc09590bcdc4beb 100644 (file)
@@ -632,8 +632,8 @@ static inline void evergreen_context_pipe_state_set_resource(struct r600_context
        block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
        if (state == NULL) {
                block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
-               radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
-               radeon_ws_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
+               r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
+               r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
                return;
        }
        block->reg[0] = state->regs[0].value;
@@ -644,18 +644,18 @@ static inline void evergreen_context_pipe_state_set_resource(struct r600_context
        block->reg[5] = state->regs[5].value;
        block->reg[6] = state->regs[6].value;
        block->reg[7] = state->regs[7].value;
-       radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
-       radeon_ws_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
+       r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
+       r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
        if (state->regs[0].bo) {
                /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
                 * we have single case btw VERTEX & TEXTURE resource
                 */
-               radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
-               radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
+               r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
+               r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
        } else {
                /* TEXTURE RESOURCE */
-               radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
-               radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
+               r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
+               r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
        }
        if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
                block->status |= R600_BLOCK_STATUS_ENABLED;
@@ -881,18 +881,18 @@ static inline void evergreen_resource_set(struct r600_context *ctx, struct r600_
        block->reg[5] = state->regs[5].value;
        block->reg[6] = state->regs[6].value;
        block->reg[7] = state->regs[7].value;
-       radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
-       radeon_ws_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
+       r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
+       r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
        if (state->regs[0].bo) {
                /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
                 * we have single case btw VERTEX & TEXTURE resource
                 */
-               radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
-               radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
+               r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
+               r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
        } else {
                /* TEXTURE RESOURCE */
-               radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
-               radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
+               r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
+               r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
        }
        if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
                block->status |= R600_BLOCK_STATUS_ENABLED;
index 0a1b3a9419045f82e16675bd89899f4bb19f9280..48727b9e6bcb67bcb6a7169d910b20c64953d7af 100644 (file)
@@ -751,7 +751,7 @@ void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_stat
                if (block->pm4_bo_index[id]) {
                        /* find relocation */
                        id = block->pm4_bo_index[id];
-                       radeon_ws_bo_reference(ctx->radeon, &block->reloc[id].bo, state->regs[i].bo);
+                       r600_bo_reference(ctx->radeon, &block->reloc[id].bo, state->regs[i].bo);
                }
                if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
                        block->status |= R600_BLOCK_STATUS_ENABLED;
@@ -770,8 +770,8 @@ static inline void r600_context_pipe_state_set_resource(struct r600_context *ctx
        block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
        if (state == NULL) {
                block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
-               radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
-               radeon_ws_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
+               r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
+               r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
                return;
        }
        block->reg[0] = state->regs[0].value;
@@ -781,18 +781,18 @@ static inline void r600_context_pipe_state_set_resource(struct r600_context *ctx
        block->reg[4] = state->regs[4].value;
        block->reg[5] = state->regs[5].value;
        block->reg[6] = state->regs[6].value;
-       radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
-       radeon_ws_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
+       r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
+       r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
        if (state->regs[0].bo) {
                /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
                 * we have single case btw VERTEX & TEXTURE resource
                 */
-               radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
-               radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
+               r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
+               r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
        } else {
                /* TEXTURE RESOURCE */
-               radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
-               radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
+               r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
+               r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
        }
        if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
                block->status |= R600_BLOCK_STATUS_ENABLED;
@@ -1151,7 +1151,7 @@ static void r600_query_result(struct r600_context *ctx, struct r600_query *query
        u32 *results;
        int i;
 
-       results = radeon_ws_bo_map(ctx->radeon, query->buffer, 0, NULL);
+       results = r600_bo_map(ctx->radeon, query->buffer, 0, NULL);
        for (i = 0; i < query->num_results; i += 4) {
                start = (u64)results[i] | (u64)results[i + 1] << 32;
                end = (u64)results[i + 2] | (u64)results[i + 3] << 32;
@@ -1159,7 +1159,7 @@ static void r600_query_result(struct r600_context *ctx, struct r600_query *query
                        query->result += end - start;
                }
        }
-       radeon_ws_bo_unmap(ctx->radeon, query->buffer);
+       r600_bo_unmap(ctx->radeon, query->buffer);
        query->num_results = 0;
 }
 
@@ -1222,7 +1222,7 @@ struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned
        query->type = query_type;
        query->buffer_size = 4096;
 
-       query->buffer = radeon_ws_bo(ctx->radeon, query->buffer_size, 1, 0);
+       query->buffer = r600_bo(ctx->radeon, query->buffer_size, 1, 0);
        if (!query->buffer) {
                free(query);
                return NULL;
@@ -1235,7 +1235,7 @@ struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned
 
 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query)
 {
-       radeon_ws_bo_reference(ctx->radeon, &query->buffer, NULL);
+       r600_bo_reference(ctx->radeon, &query->buffer, NULL);
        LIST_DEL(&query->list);
        free(query);
 }
index fdca6f01e84954fdd767f9a2447aed0ab7a3a3f9..4bd2c278bc78530a16a500f1ffa53ea2351b8792 100644 (file)
@@ -65,7 +65,7 @@ struct radeon_bo {
        void                            *data;
 };
 
-struct radeon_ws_bo {
+struct r600_bo {
        struct pipe_reference           reference;
        struct pb_buffer                *pb;
 };
@@ -93,9 +93,9 @@ struct pb_manager *radeon_bo_pbmgr_create(struct radeon *radeon);
 struct pb_buffer *radeon_bo_pb_create_buffer_from_handle(struct pb_manager *_mgr,
                                                         uint32_t handle);
 
-/* radeon_ws_bo.c */
-unsigned radeon_ws_bo_get_handle(struct radeon_ws_bo *bo);
-unsigned radeon_ws_bo_get_size(struct radeon_ws_bo *bo);
+/* r600_bo.c */
+unsigned r600_bo_get_handle(struct r600_bo *bo);
+unsigned r600_bo_get_size(struct r600_bo *bo);
 
 #define CTX_RANGE_ID(ctx, offset) (((offset) >> (ctx)->hash_shift) & 255)
 #define CTX_BLOCK_ID(ctx, offset) ((offset) & ((1 << (ctx)->hash_shift) - 1))
index ed3b4e72bf934f4b724f473fd24e88819944fa51..a502c7e2521eae2006dcca7c2edbc9420b888cc7 100644 (file)
 #include <pipebuffer/pb_bufmgr.h>
 #include "r600_priv.h"
 
-struct radeon_ws_bo *radeon_ws_bo(struct radeon *radeon,
+struct r600_bo *r600_bo(struct radeon *radeon,
                                  unsigned size, unsigned alignment, unsigned usage)
 {
-       struct radeon_ws_bo *ws_bo = calloc(1, sizeof(struct radeon_ws_bo));
+       struct r600_bo *ws_bo = calloc(1, sizeof(struct r600_bo));
        struct pb_desc desc;
        struct pb_manager *man;
 
@@ -55,10 +55,10 @@ struct radeon_ws_bo *radeon_ws_bo(struct radeon *radeon,
        return ws_bo;
 }
 
-struct radeon_ws_bo *radeon_ws_bo_handle(struct radeon *radeon,
+struct r600_bo *r600_bo_handle(struct radeon *radeon,
                                         unsigned handle)
 {
-       struct radeon_ws_bo *ws_bo = calloc(1, sizeof(struct radeon_ws_bo));
+       struct r600_bo *ws_bo = calloc(1, sizeof(struct r600_bo));
 
        ws_bo->pb = radeon_bo_pb_create_buffer_from_handle(radeon->kman, handle);
        if (!ws_bo->pb) {
@@ -69,35 +69,35 @@ struct radeon_ws_bo *radeon_ws_bo_handle(struct radeon *radeon,
        return ws_bo;
 }
 
-void *radeon_ws_bo_map(struct radeon *radeon, struct radeon_ws_bo *bo, unsigned usage, void *ctx)
+void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx)
 {
        return pb_map(bo->pb, usage, ctx);
 }
 
-void radeon_ws_bo_unmap(struct radeon *radeon, struct radeon_ws_bo *bo)
+void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo)
 {
        pb_unmap(bo->pb);
 }
 
-static void radeon_ws_bo_destroy(struct radeon *radeon, struct radeon_ws_bo *bo)
+static void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo)
 {
        if (bo->pb)
                pb_reference(&bo->pb, NULL);
        free(bo);
 }
 
-void radeon_ws_bo_reference(struct radeon *radeon, struct radeon_ws_bo **dst,
-                           struct radeon_ws_bo *src)
+void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst,
+                           struct r600_bo *src)
 {
-       struct radeon_ws_bo *old = *dst;
+       struct r600_bo *old = *dst;
                
        if (pipe_reference(&(*dst)->reference, &src->reference)) {
-               radeon_ws_bo_destroy(radeon, old);
+               r600_bo_destroy(radeon, old);
        }
        *dst = src;
 }
 
-unsigned radeon_ws_bo_get_handle(struct radeon_ws_bo *pb_bo)
+unsigned r600_bo_get_handle(struct r600_bo *pb_bo)
 {
        struct radeon_bo *bo;
 
@@ -108,7 +108,7 @@ unsigned radeon_ws_bo_get_handle(struct radeon_ws_bo *pb_bo)
        return bo->handle;
 }
 
-unsigned radeon_ws_bo_get_size(struct radeon_ws_bo *pb_bo)
+unsigned r600_bo_get_size(struct r600_bo *pb_bo)
 {
        struct radeon_bo *bo;