radv: remove useless sync before CmdClear{Color,DepthStencil}Image()

We don't need to flush anything before these two commands as well.
This is because they have to be externally synchronized, so the
app should have called CmdPipelineBarrier() prior to that and the
driver should have flushed the caches.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index bf88d3a84d96ee22bb8fb143fbdf90d8682d8e4d..f2f5cb32eb9726e489a70f2732aaba3559f27f18 100644 (file)
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -948,9 +948,7 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
                cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
                *pre_flush |= cmd_buffer->state.flush_bits;
-       } else
-               cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
-                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
+       }
 
        if (htile_mask == UINT_MAX) {
                /* Clear the whole HTILE buffer. */
@@ -1402,9 +1400,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
                cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
                                                 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
                *pre_flush |= cmd_buffer->state.flush_bits;
-       } else
-               cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
-                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
+       }
 
        cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);