(no commit message)

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index 9eeb514ffcc814c0fc7dc6318678b86eb84a7e38..0d54ff69ff8da7b554dd3c9a6164572357af4a78 100644 (file)
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -25,7 +25,7 @@ Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR` instruction and to the
 Prefix instruction.  More advanced features are similar to the Z80
 `CPIR` instruction. If viewed one-dimensionally as an actual Vector ISA it introduces
 over 1.5 million 64-bit Vector instructions.  SVP64, the instruction
-format, is therefore best viewed as an orthogonal RISC-style "Prefixing"
+format, is therefore best viewed as an orthogonal RISC-paradigm "Prefixing"
 subsystem instead.
 
 Except where explicitly stated all bit numbers remain as in the rest of