// Remove all AND, NOT, and ABC box instances
// in preparation for stitching mapped_mod in
- pool<IdString> erased_boxes;
+ dict<IdString, decltype(RTLIL::Cell::parameters)> erased_boxes;
for (auto it = module->cells_.begin(); it != module->cells_.end(); ) {
RTLIL::Cell* cell = it->second;
if (cell->type.in("$_AND_", "$_NOT_")) {
}
RTLIL::Module* box_module = design->module(cell->type);
if (box_module && box_module->attributes.count("\\abc_box_id")) {
- erased_boxes.insert(it->first);
+ erased_boxes.insert(std::make_pair(it->first, std::move(cell->parameters)));
it = module->cells_.erase(it);
continue;
}
continue;
}
}
- else
- log_assert(erased_boxes.count(c->name));
+ else {
+ auto it = erased_boxes.find(c->name);
+ log_assert(it != erased_boxes.end());
+ c->parameters = std::move(it->second);
+ }
RTLIL::Cell* cell = module->addCell(remap_name(c->name), c->type);
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
continue;
}
- if (mod->attributes.count("\\abc_box_id"))
- continue;
-
assign_map.set(mod);
signal_init.clear();