Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp

diff --cc techlibs/xilinx/cells_sim.v
Simple merge

diff --cc techlibs/xilinx/synth_xilinx.cc
index 26d01ce4013f485b609419621f810312e521c6a5,2bd8570ec7936907998e6269e62b45c085231fd2..5e491b86bc09d1095006392c2f717f0e09dd5a60
--- 1/techlibs/xilinx/synth_xilinx.cc
--- 2/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -107,7 -118,9 +118,8 @@@ struct SynthXilinxPass : public ScriptP
        }
  
        std::string top_opt, edif_file, blif_file, family;
-       bool flatten, retime, vpr, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, abc9;
 -      bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, nodsp, abc9;
+       bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, abc9;
+       bool flatten_before_abc;
        int widemux;
  
        void clear_flags() YS_OVERRIDE