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diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn
index 78b54153a928eefe675b04cb3c8c6319b3261eeb..12b81385798ed9a523f3f17738d9badb2f33025d 100644 (file)
--- a/docs/pinmux.mdwn
+++ b/docs/pinmux.mdwn
@@ -24,7 +24,11 @@ absolutely out of the question.
 Yet, the expectation from the market is to be able to fit 1,000++
 pins worth of peripherals into only 200 to 400 worth of actual
 IO Pads. The solution here: a GPIO Pinmux, described in some
-detail here 
+detail here <https://ftp.libre-soc.org/Pin_Control_Subsystem_Overview.pdf>
+
+This page goes over the details and issues involved in creating
+an ASIC that combines **both** JTAG Boundary Scan **and** GPIO
+Muxing, down to layout considerations using coriolis2.
 
 <img src="https://libre-soc.org/shakti/m_class/JTAG/jtag-block.jpg"
   width=600 />