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diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 24bdfd3f2e4d83d9ed6964d05d6c46103645ae69..8221cdb69c94eb78bb7535d5061a7c97ec39cf4e 100644 (file)
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -89,11 +89,11 @@ code sigB clock clock_pol
 endcode
 
 match ffFJKG
+       // Ensure pipeline register is not already used
        if mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
        select ffFJKG->type.in($dff)
        select nusers(port(ffFJKG, \D)) == 2
        index <SigSpec> port(ffFJKG, \D) === sigH
-       // Ensure pipeline register is not already used
        optional
 endmatch