split out instructions from openpower/isa/svfparith.mdwn

diff --git a/openpower/isa/svfparith.mdwn b/openpower/isa/svfparith.mdwn
index b6066f8fb2715ab71af6f6a5d172a501feee9572..dce49e0973f1934b623a0e393cdd6ed27f5e1460 100644 (file)
--- a/openpower/isa/svfparith.mdwn
+++ b/openpower/isa/svfparith.mdwn
@@ -7,254 +7,28 @@
 
 <!-- PLEASE NOTE THESE ARE UNAPPROVED AND DRAFT, NOT SUBMITTED TO OPF ISA WG -->
 
-# [DRAFT] Floating Add FFT/DCT [Single]
+[[!inline pagenames="openpower/isa/svfparith/ffadds" raw="yes"]]
 
-A-Form
+[[!inline pagenames="openpower/isa/svfparith/ffadd" raw="yes"]]
 
-* ffadds FRT,FRA,FRB (Rc=0)
-* ffadds. FRT,FRA,FRB (Rc=1)
+[[!inline pagenames="openpower/isa/svfparith/ffsubs" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/svfparith/ffsub" raw="yes"]]
 
-    FRT <- FPADD32(FRA, FRB)
-    FRS <- FPSUB32(FRB, FRA)
+[[!inline pagenames="openpower/isa/svfparith/ffmuls" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/svfparith/ffmul" raw="yes"]]
 
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI
-    CR1          (if Rc=1)
+[[!inline pagenames="openpower/isa/svfparith/ffdivs" raw="yes"]]
 
-# [DRAFT] Floating Add FFT/DCT [Double]
+[[!inline pagenames="openpower/isa/svfparith/ffdiv" raw="yes"]]
 
-A-Form
+[[!inline pagenames="openpower/isa/svfparith/fdmadds" raw="yes"]]
 
-* ffadd FRT,FRA,FRB (Rc=0)
-* ffadd. FRT,FRA,FRB (Rc=1)
+[[!inline pagenames="openpower/isa/svfparith/ffmadds" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/svfparith/ffmsubs" raw="yes"]]
 
-    FRT <- FPADD64(FRA, FRB)
-    FRS <- FPSUB64(FRB, FRA)
+[[!inline pagenames="openpower/isa/svfparith/ffnmadds" raw="yes"]]
 
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating Subtract FFT/DCT [Single]
-
-A-Form
-
-* ffsubs FRT,FRA,FRB (Rc=0)
-* ffsubs. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- FPSUB32(FRB, FRA)
-    FRS <- FPADD32(FRA, FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating Subtract FFT/DCT [Double]
-
-A-Form
-
-* ffsub FRT,FRA,FRB (Rc=0)
-* ffsub. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- FPSUB64(FRB, FRA)
-    FRS <- FPADD64(FRA, FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating Multiply FFT/DCT [Single]
-
-A-Form
-
-* ffmuls FRT,FRA,FRC (Rc=0)
-* ffmuls. FRT,FRA,FRC (Rc=1)
-
-Pseudo-code:
-
-    FRT <- FPMUL32(FRA, FRC)
-    FRS <- FPMUL32(FRA, FRC, -1)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating Multiply FFT/DCT [Double]
-
-A-Form
-
-* ffmul FRT,FRA,FRC (Rc=0)
-* ffmul. FRT,FRA,FRC (Rc=1)
-
-Pseudo-code:
-
-    FRT <- FPMUL64(FRA, FRC)
-    FRS <- FPMUL64(FRA, FRC, -1)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating Divide FFT/DCT [Single]
-
-A-Form
-
-* ffdivs FRT,FRA,FRB (Rc=0)
-* ffdivs. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- FPDIV32(FRA, FRB)
-    FRS <- FPDIV32(FRA, FRB, -1)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating Divide FFT/DCT [Double]
-
-A-Form
-
-* ffdiv FRT,FRA,FRB (Rc=0)
-* ffdiv. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- FPDIV64(FRA, FRB)
-    FRS <- FPDIV64(FRA, FRB, -1)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating Twin Multiply-Add DCT [Single]
-
-DCT-Form
-
-* fdmadds FRT,FRA,FRB (Rc=0)
-* fdmadds. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRS <- FPADD32(FRT, FRB)
-    sub <- FPSUB32(FRT, FRB)
-    FRT <- FPMUL32(FRA, sub)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating Multiply-Add FFT [Single]
-
-A-Form
-
-* ffmadds FRT,FRA,FRB (Rc=0)
-* ffmadds. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    tmp <- FRT
-    FRT <- FPMULADD32(tmp, FRA, FRB, 1, 1)
-    FRS <- FPMULADD32(tmp, FRA, FRB, -1, 1)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating Multiply-Sub FFT [Single]
-
-A-Form
-
-* ffmsubs FRT,FRA,FRB (Rc=0)
-* ffmsubs. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    tmp <- FRT
-    FRT <- FPMULADD32(tmp, FRA, FRB, 1, -1)
-    FRS <- FPMULADD32(tmp, FRA, FRB, -1, -1)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating Negative Multiply-Add FFT [Single]
-
-A-Form
-
-* ffnmadds FRT,FRA,FRB (Rc=0)
-* ffnmadds. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    tmp <- FRT
-    FRT <- FPMULADD32(tmp, FRA, FRB, -1, -1)
-    FRS <- FPMULADD32(tmp, FRA, FRB, 1, -1)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating Negative Multiply-Sub FFT [Single]
-
-A-Form
-
-* ffnmsubs FRT,FRA,FRB (Rc=0)
-* ffnmsubs. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    tmp <- FRT
-    FRT <- FPMULADD32(tmp, FRA, FRB, -1, 1)
-    FRS <- FPMULADD32(tmp, FRA, FRB, 1, 1)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
+[[!inline pagenames="openpower/isa/svfparith/ffnmsubs" raw="yes"]]

diff --git a/openpower/isa/svfparith/fdmadds.mdwn b/openpower/isa/svfparith/fdmadds.mdwn
new file mode 100644 (file)
index 0000000..b52eb6f
--- /dev/null
+++ b/openpower/isa/svfparith/fdmadds.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating Twin Multiply-Add DCT [Single]
+
+DCT-Form
+
+* fdmadds FRT,FRA,FRB (Rc=0)
+* fdmadds. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/svfparith/fdmadds_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/svfparith/fdmadds_code.mdwn b/openpower/isa/svfparith/fdmadds_code.mdwn
new file mode 100644 (file)
index 0000000..4a7ef3a
--- /dev/null
+++ b/openpower/isa/svfparith/fdmadds_code.mdwn
@@ -0,0 +1,3 @@
+    FRS <- FPADD32(FRT, FRB)
+    sub <- FPSUB32(FRT, FRB)
+    FRT <- FPMUL32(FRA, sub)

diff --git a/openpower/isa/svfparith/ffadd.mdwn b/openpower/isa/svfparith/ffadd.mdwn
new file mode 100644 (file)
index 0000000..18f79dd
--- /dev/null
+++ b/openpower/isa/svfparith/ffadd.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating Add FFT/DCT [Double]
+
+A-Form
+
+* ffadd FRT,FRA,FRB (Rc=0)
+* ffadd. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/svfparith/ffadd_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)

diff --git a/openpower/isa/svfparith/ffadd_code.mdwn b/openpower/isa/svfparith/ffadd_code.mdwn
new file mode 100644 (file)
index 0000000..a4980ba
--- /dev/null
+++ b/openpower/isa/svfparith/ffadd_code.mdwn
@@ -0,0 +1,2 @@
+    FRT <- FPADD64(FRA, FRB)
+    FRS <- FPSUB64(FRB, FRA)

diff --git a/openpower/isa/svfparith/ffadds.mdwn b/openpower/isa/svfparith/ffadds.mdwn
new file mode 100644 (file)
index 0000000..526fe3c
--- /dev/null
+++ b/openpower/isa/svfparith/ffadds.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating Add FFT/DCT [Single]
+
+A-Form
+
+* ffadds FRT,FRA,FRB (Rc=0)
+* ffadds. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/svfparith/ffadds_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)

diff --git a/openpower/isa/svfparith/ffadds_code.mdwn b/openpower/isa/svfparith/ffadds_code.mdwn
new file mode 100644 (file)
index 0000000..6619b67
--- /dev/null
+++ b/openpower/isa/svfparith/ffadds_code.mdwn
@@ -0,0 +1,2 @@
+    FRT <- FPADD32(FRA, FRB)
+    FRS <- FPSUB32(FRB, FRA)

diff --git a/openpower/isa/svfparith/ffdiv.mdwn b/openpower/isa/svfparith/ffdiv.mdwn
new file mode 100644 (file)
index 0000000..e5941de
--- /dev/null
+++ b/openpower/isa/svfparith/ffdiv.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating Divide FFT/DCT [Double]
+
+A-Form
+
+* ffdiv FRT,FRA,FRB (Rc=0)
+* ffdiv. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/svfparith/ffdiv_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)

diff --git a/openpower/isa/svfparith/ffdiv_code.mdwn b/openpower/isa/svfparith/ffdiv_code.mdwn
new file mode 100644 (file)
index 0000000..38d4736
--- /dev/null
+++ b/openpower/isa/svfparith/ffdiv_code.mdwn
@@ -0,0 +1,2 @@
+    FRT <- FPDIV64(FRA, FRB)
+    FRS <- FPDIV64(FRA, FRB, -1)

diff --git a/openpower/isa/svfparith/ffdivs.mdwn b/openpower/isa/svfparith/ffdivs.mdwn
new file mode 100644 (file)
index 0000000..15a2a5b
--- /dev/null
+++ b/openpower/isa/svfparith/ffdivs.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating Divide FFT/DCT [Single]
+
+A-Form
+
+* ffdivs FRT,FRA,FRB (Rc=0)
+* ffdivs. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/svfparith/ffdivs_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)

diff --git a/openpower/isa/svfparith/ffdivs_code.mdwn b/openpower/isa/svfparith/ffdivs_code.mdwn
new file mode 100644 (file)
index 0000000..6ff2836
--- /dev/null
+++ b/openpower/isa/svfparith/ffdivs_code.mdwn
@@ -0,0 +1,2 @@
+    FRT <- FPDIV32(FRA, FRB)
+    FRS <- FPDIV32(FRA, FRB, -1)

diff --git a/openpower/isa/svfparith/ffmadds.mdwn b/openpower/isa/svfparith/ffmadds.mdwn
new file mode 100644 (file)
index 0000000..281e20e
--- /dev/null
+++ b/openpower/isa/svfparith/ffmadds.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating Multiply-Add FFT [Single]
+
+A-Form
+
+* ffmadds FRT,FRA,FRB (Rc=0)
+* ffmadds. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/svfparith/ffmadds_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/svfparith/ffmadds_code.mdwn b/openpower/isa/svfparith/ffmadds_code.mdwn
new file mode 100644 (file)
index 0000000..dad9f5b
--- /dev/null
+++ b/openpower/isa/svfparith/ffmadds_code.mdwn
@@ -0,0 +1,3 @@
+    tmp <- FRT
+    FRT <- FPMULADD32(tmp, FRA, FRB, 1, 1)
+    FRS <- FPMULADD32(tmp, FRA, FRB, -1, 1)

diff --git a/openpower/isa/svfparith/ffmsubs.mdwn b/openpower/isa/svfparith/ffmsubs.mdwn
new file mode 100644 (file)
index 0000000..834f24f
--- /dev/null
+++ b/openpower/isa/svfparith/ffmsubs.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating Multiply-Sub FFT [Single]
+
+A-Form
+
+* ffmsubs FRT,FRA,FRB (Rc=0)
+* ffmsubs. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/svfparith/ffmsubs_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/svfparith/ffmsubs_code.mdwn b/openpower/isa/svfparith/ffmsubs_code.mdwn
new file mode 100644 (file)
index 0000000..77658ab
--- /dev/null
+++ b/openpower/isa/svfparith/ffmsubs_code.mdwn
@@ -0,0 +1,3 @@
+    tmp <- FRT
+    FRT <- FPMULADD32(tmp, FRA, FRB, 1, -1)
+    FRS <- FPMULADD32(tmp, FRA, FRB, -1, -1)

diff --git a/openpower/isa/svfparith/ffmul.mdwn b/openpower/isa/svfparith/ffmul.mdwn
new file mode 100644 (file)
index 0000000..06125dd
--- /dev/null
+++ b/openpower/isa/svfparith/ffmul.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating Multiply FFT/DCT [Double]
+
+A-Form
+
+* ffmul FRT,FRA,FRC (Rc=0)
+* ffmul. FRT,FRA,FRC (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/svfparith/ffmul_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)

diff --git a/openpower/isa/svfparith/ffmul_code.mdwn b/openpower/isa/svfparith/ffmul_code.mdwn
new file mode 100644 (file)
index 0000000..7a33c99
--- /dev/null
+++ b/openpower/isa/svfparith/ffmul_code.mdwn
@@ -0,0 +1,2 @@
+    FRT <- FPMUL64(FRA, FRC)
+    FRS <- FPMUL64(FRA, FRC, -1)

diff --git a/openpower/isa/svfparith/ffmuls.mdwn b/openpower/isa/svfparith/ffmuls.mdwn
new file mode 100644 (file)
index 0000000..5e11e2e
--- /dev/null
+++ b/openpower/isa/svfparith/ffmuls.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating Multiply FFT/DCT [Single]
+
+A-Form
+
+* ffmuls FRT,FRA,FRC (Rc=0)
+* ffmuls. FRT,FRA,FRC (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/svfparith/ffmuls_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)

diff --git a/openpower/isa/svfparith/ffmuls_code.mdwn b/openpower/isa/svfparith/ffmuls_code.mdwn
new file mode 100644 (file)
index 0000000..61b9a42
--- /dev/null
+++ b/openpower/isa/svfparith/ffmuls_code.mdwn
@@ -0,0 +1,2 @@
+    FRT <- FPMUL32(FRA, FRC)
+    FRS <- FPMUL32(FRA, FRC, -1)

diff --git a/openpower/isa/svfparith/ffnmadds.mdwn b/openpower/isa/svfparith/ffnmadds.mdwn
new file mode 100644 (file)
index 0000000..71a205b
--- /dev/null
+++ b/openpower/isa/svfparith/ffnmadds.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating Negative Multiply-Add FFT [Single]
+
+A-Form
+
+* ffnmadds FRT,FRA,FRB (Rc=0)
+* ffnmadds. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/svfparith/ffnmadds_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/svfparith/ffnmadds_code.mdwn b/openpower/isa/svfparith/ffnmadds_code.mdwn
new file mode 100644 (file)
index 0000000..7835a67
--- /dev/null
+++ b/openpower/isa/svfparith/ffnmadds_code.mdwn
@@ -0,0 +1,3 @@
+    tmp <- FRT
+    FRT <- FPMULADD32(tmp, FRA, FRB, -1, -1)
+    FRS <- FPMULADD32(tmp, FRA, FRB, 1, -1)

diff --git a/openpower/isa/svfparith/ffnmsubs.mdwn b/openpower/isa/svfparith/ffnmsubs.mdwn
new file mode 100644 (file)
index 0000000..a453efe
--- /dev/null
+++ b/openpower/isa/svfparith/ffnmsubs.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating Negative Multiply-Sub FFT [Single]
+
+A-Form
+
+* ffnmsubs FRT,FRA,FRB (Rc=0)
+* ffnmsubs. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/svfparith/ffnmsubs_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/svfparith/ffnmsubs_code.mdwn b/openpower/isa/svfparith/ffnmsubs_code.mdwn
new file mode 100644 (file)
index 0000000..0d7f4c2
--- /dev/null
+++ b/openpower/isa/svfparith/ffnmsubs_code.mdwn
@@ -0,0 +1,3 @@
+    tmp <- FRT
+    FRT <- FPMULADD32(tmp, FRA, FRB, -1, 1)
+    FRS <- FPMULADD32(tmp, FRA, FRB, 1, 1)

diff --git a/openpower/isa/svfparith/ffsub.mdwn b/openpower/isa/svfparith/ffsub.mdwn
new file mode 100644 (file)
index 0000000..fd3bfd9
--- /dev/null
+++ b/openpower/isa/svfparith/ffsub.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating Subtract FFT/DCT [Double]
+
+A-Form
+
+* ffsub FRT,FRA,FRB (Rc=0)
+* ffsub. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/svfparith/ffsub_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)

diff --git a/openpower/isa/svfparith/ffsub_code.mdwn b/openpower/isa/svfparith/ffsub_code.mdwn
new file mode 100644 (file)
index 0000000..8ea1fd7
--- /dev/null
+++ b/openpower/isa/svfparith/ffsub_code.mdwn
@@ -0,0 +1,2 @@
+    FRT <- FPSUB64(FRB, FRA)
+    FRS <- FPADD64(FRA, FRB)

diff --git a/openpower/isa/svfparith/ffsubs.mdwn b/openpower/isa/svfparith/ffsubs.mdwn
new file mode 100644 (file)
index 0000000..f0ffb96
--- /dev/null
+++ b/openpower/isa/svfparith/ffsubs.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating Subtract FFT/DCT [Single]
+
+A-Form
+
+* ffsubs FRT,FRA,FRB (Rc=0)
+* ffsubs. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/svfparith/ffsubs_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)

diff --git a/openpower/isa/svfparith/ffsubs_code.mdwn b/openpower/isa/svfparith/ffsubs_code.mdwn
new file mode 100644 (file)
index 0000000..f27f380
--- /dev/null
+++ b/openpower/isa/svfparith/ffsubs_code.mdwn
@@ -0,0 +1,2 @@
+    FRT <- FPSUB32(FRB, FRA)
+    FRS <- FPADD32(FRA, FRB)