x86-64: adjust MOVQ to/from SReg attributes

It is unclear to me why the corresponding MOV (no Q suffix) can be
issued without REX.W, but MOVQ has to have that prefix (bit). Add
NoRex64 and in exchange drop Size64.

diff --git a/gas/testsuite/gas/i386/x86-64-segment.l b/gas/testsuite/gas/i386/x86-64-segment.l
index 4056fde869e741908070c50af5d090ba1c6a5dcd..031b0cb484a598938ab03dfbb465aaf90d875d43 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-segment.l
+++ b/gas/testsuite/gas/i386/x86-64-segment.l
@@ -5,8 +5,15 @@
    5 0002 8C18                 mov     %ds,\(%rax\)
    6 0004 8E18                 movw    \(%rax\),%ds
    7 0006 8E18                 mov     \(%rax\),%ds
-   8                   # test segment reg insns with REX
-   9 0008 488CD8               movq    %ds,%rax
-  10 000b 488ED8               movq    %rax,%ds
-  11                           # Force a good alignment.
-  12 000e 0000                 .p2align        4,0
+   8                   # test segment reg insns with avoided REX
+   9 0008 8CD8                 mov     %ds,%rax
+  10 000a 8CD8                 movq    %ds,%rax
+  11 000c 8ED8                 mov     %rax,%ds
+  12 000e 8ED8                 movq    %rax,%ds
+  13                   # test segment reg insns with REX
+  14 0010 418CD8               mov     %ds,%r8
+  15 0013 418CD8               movq    %ds,%r8
+  16 0016 418ED8               mov     %r8,%ds
+  17 0019 418ED8               movq    %r8,%ds
+  18                           # Force a good alignment.
+  19 001c 0+ + *\.p2align      4,0

diff --git a/gas/testsuite/gas/i386/x86-64-segment.s b/gas/testsuite/gas/i386/x86-64-segment.s
index 16fcd76190607ab9e9c0ca269ab593439d2beffd..a3f3205e7fd275562bf9f5c1d4654d97dbb5fcf9 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-segment.s
+++ b/gas/testsuite/gas/i386/x86-64-segment.s
@@ -5,8 +5,15 @@
        mov     %ds,(%rax)
        movw    (%rax),%ds
        mov     (%rax),%ds
-# test segment reg insns with REX
+# test segment reg insns with avoided REX
+       mov     %ds,%rax
        movq    %ds,%rax
+       mov     %rax,%ds
        movq    %rax,%ds
+# test segment reg insns with REX
+       mov     %ds,%r8
+       movq    %ds,%r8
+       mov     %r8,%ds
+       movq    %r8,%ds
        # Force a good alignment.
        .p2align        4,0

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index c345332276ce7b6bdfa386ee31cd696fedb905c3..37704f061ce72f391d3c5956e3cca7e90af6a56f 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -148,7 +148,7 @@ movq, 0xb8, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf
 // implementation defined value is zero).
 mov, 0x8c, None, 0, RegMem|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { SReg, Reg16|Reg32|Reg64 }
 mov, 0x8c, None, 0, D|Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg, Word|Unspecified|BaseIndex }
-movq, 0x8c, None, Cpu64, D|RegMem|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg, Reg64 }
+movq, 0x8c, None, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { SReg, Reg64 }
 mov, 0x8e, None, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg16|Reg32|Reg64, SReg }
 // Move to/from control debug registers.  In the 16 or 32bit modes
 // they are 32bit.  In the 64bit mode they are 64bit.

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 64ee8f6edd7682ae60fefe30d651a3043a910e34..d2665f1a46f079eea1e80ecf0cf68fd5c400a785 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -323,8 +323,8 @@ const insn_template i386_optab[] =
       { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
          0, 0, 0, 0, 0, 0 } } } },
   { "movq", 0x8c, 2, None,
-    { 1, 0, 0, 1, 0, 0, 0, 3, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0,
-      1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0,
+      1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,