set_feature (FEATURE_AVX5124FMAPS);
if (edx & bit_AVX512VP2INTERSECT)
set_feature (FEATURE_AVX512VP2INTERSECT);
+ if (edx & bit_UINTR)
+ set_feature (FEATURE_UINTR);
__cpuid_count (7, 1, eax, ebx, ecx, edx);
if (eax & bit_AVX512BF16)
#define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
#define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE
#define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK
+#define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR
/* Define a set of ISAs which aren't available when a given ISA is
disabled. MMX and SSE ISAs are handled separately. */
#define OPTION_MASK_ISA2_AMX_TILE_UNSET OPTION_MASK_ISA2_AMX_TILE
#define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8
#define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16
+#define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
}
return true;
+ case OPT_muintr:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_UINTR_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_UINTR_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_UNSET;
+ }
+ return true;
+
case OPT_mavx5124fmaps:
if (value)
{
FEATURE_AMX_TILE,
FEATURE_AMX_INT8,
FEATURE_AMX_BF16,
+ FEATURE_UINTR,
CPU_FEATURE_MAX
};
ISA_NAMES_TABLE_ENTRY("amx-tile", FEATURE_AMX_TILE, P_NONE, "-mamx-tile")
ISA_NAMES_TABLE_ENTRY("amx-int8", FEATURE_AMX_INT8, P_NONE, "-mamx-int8")
ISA_NAMES_TABLE_ENTRY("amx-bf16", FEATURE_AMX_BF16, P_NONE, "-mamx-bf16")
+ ISA_NAMES_TABLE_ENTRY("uintr", FEATURE_UINTR, P_NONE, "-muintr")
ISA_NAMES_TABLE_END
avx512bf16intrin.h enqcmdintrin.h serializeintrin.h
avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h
tsxldtrkintrin.h amxtileintrin.h amxint8intrin.h
- amxbf16intrin.h x86gprintrin.h"
+ amxbf16intrin.h x86gprintrin.h uintrintrin.h"
;;
x86_64-*-*)
cpu_type=i386
avx512bf16intrin.h enqcmdintrin.h serializeintrin.h
avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h
tsxldtrkintrin.h amxtileintrin.h amxint8intrin.h
- amxbf16intrin.h x86gprintrin.h"
+ amxbf16intrin.h x86gprintrin.h uintrintrin.h"
;;
ia64-*-*)
extra_headers=ia64intrin.h
#define bit_AVX5124FMAPS (1 << 3)
#define bit_AVX512VP2INTERSECT (1 << 8)
#define bit_IBT (1 << 20)
+#define bit_UINTR (1 << 5)
#define bit_PCONFIG (1 << 18)
#define bit_SERIALIZE (1 << 14)
#define bit_TSXLDTRK (1 << 16)
DEF_FUNCTION_TYPE (UINT)
DEF_FUNCTION_TYPE (USHORT)
DEF_FUNCTION_TYPE (INT)
+DEF_FUNCTION_TYPE (UINT8)
DEF_FUNCTION_TYPE (VOID)
DEF_FUNCTION_TYPE (PVOID)
BDESC (0, OPTION_MASK_ISA2_TSXLDTRK, CODE_FOR_xsusldtrk, "__builtin_ia32_xsusldtrk", IX86_BUILTIN_XSUSLDTRK, UNKNOWN, (int) VOID_FTYPE_VOID)
BDESC (0, OPTION_MASK_ISA2_TSXLDTRK, CODE_FOR_xresldtrk, "__builtin_ia32_xresldtrk", IX86_BUILTIN_XRESLDTRK, UNKNOWN, (int) VOID_FTYPE_VOID)
+/* UINTR. */
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_UINTR, CODE_FOR_clui, "__builtin_ia32_clui", IX86_BUILTIN_CLUI, UNKNOWN, (int) VOID_FTYPE_VOID)
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_UINTR, CODE_FOR_stui, "__builtin_ia32_stui", IX86_BUILTIN_STUI, UNKNOWN, (int) VOID_FTYPE_VOID)
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_UINTR, CODE_FOR_senduipi, "__builtin_ia32_senduipi", IX86_BUILTIN_SENDUIPI, UNKNOWN, (int) VOID_FTYPE_UINT64)
+
BDESC_END (SPECIAL_ARGS, ARGS)
/* Builtins with variable number of arguments. */
def_builtin (0, OPTION_MASK_ISA2_WAITPKG, "__builtin_ia32_tpause",
UINT8_FTYPE_UNSIGNED_UINT64, IX86_BUILTIN_TPAUSE);
+ /* UINTR. */
+ def_builtin (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_UINTR,
+ "__builtin_ia32_testui",
+ UINT8_FTYPE_VOID, IX86_BUILTIN_TESTUI);
+
/* CLDEMOTE. */
def_builtin (0, OPTION_MASK_ISA2_CLDEMOTE, "__builtin_ia32_cldemote",
VOID_FTYPE_PCVOID, IX86_BUILTIN_CLDEMOTE);
IX86_BUILTIN_UMONITOR,
IX86_BUILTIN_UMWAIT,
IX86_BUILTIN_TPAUSE,
+ IX86_BUILTIN_TESTUI,
IX86_BUILTIN_CLZERO,
IX86_BUILTIN_CLDEMOTE,
IX86_BUILTIN_VEC_INIT_V2SI,
def_or_undef (parse_in, "__LAHF_SAHF__");
if (isa_flag2 & OPTION_MASK_ISA2_MOVBE)
def_or_undef (parse_in, "__MOVBE__");
+ if (isa_flag2 & OPTION_MASK_ISA2_UINTR)
+ def_or_undef (parse_in, "__UINTR__");
if (TARGET_IAMCU)
{
case USHORT_FTYPE_VOID:
case UINT64_FTYPE_VOID:
case UINT_FTYPE_VOID:
+ case UINT8_FTYPE_VOID:
case UNSIGNED_FTYPE_VOID:
nargs = 0;
klass = load;
return target;
+ case IX86_BUILTIN_TESTUI:
+ emit_insn (gen_testui ());
+
+ if (target == 0
+ || !register_operand (target, QImode))
+ target = gen_reg_rtx (QImode);
+
+ pat = gen_rtx_LTU (QImode, gen_rtx_REG (CCCmode, FLAGS_REG),
+ const0_rtx);
+ emit_insn (gen_rtx_SET (target, pat));
+
+ return target;
+
case IX86_BUILTIN_CLZERO:
arg0 = CALL_EXPR_ARG (exp, 0);
op0 = expand_normal (arg0);
{ "-mtsxldtrk", OPTION_MASK_ISA2_TSXLDTRK },
{ "-mamx-tile", OPTION_MASK_ISA2_AMX_TILE },
{ "-mamx-int8", OPTION_MASK_ISA2_AMX_INT8 },
- { "-mamx-bf16", OPTION_MASK_ISA2_AMX_BF16 }
+ { "-mamx-bf16", OPTION_MASK_ISA2_AMX_BF16 },
+ { "-muintr", OPTION_MASK_ISA2_UINTR }
};
static struct ix86_target_opts isa_opts[] =
{
IX86_ATTR_ISA ("movdir64b", OPT_mmovdir64b),
IX86_ATTR_ISA ("waitpkg", OPT_mwaitpkg),
IX86_ATTR_ISA ("cldemote", OPT_mcldemote),
+ IX86_ATTR_ISA ("uintr", OPT_muintr),
IX86_ATTR_ISA ("ptwrite", OPT_mptwrite),
IX86_ATTR_ISA ("avx512bf16", OPT_mavx512bf16),
IX86_ATTR_ISA ("enqcmd", OPT_menqcmd),
opts->x_ix86_stringop_alg = no_stringop;
}
+ if (TARGET_UINTR && !TARGET_64BIT)
+ error ("%<-muintr%> not supported for 32-bit code");
+
if (!opts->x_ix86_arch_string)
opts->x_ix86_arch_string
= TARGET_64BIT_P (opts->x_ix86_isa_flags)
#define TARGET_AMX_INT8_P(x) TARGET_ISA2_AMX_INT8(x)
#define TARGET_AMX_BF16 TARGET_ISA2_AMX_BF16
#define TARGET_AMX_BF16_P(x) TARGET_ISA2_AMX_BF16(x)
+#define TARGET_UINTR TARGET_ISA2_UINTR
+#define TARGET_UINTR_P(x) TARGET_ISA2_UINTR_P(x)
#define TARGET_LP64 TARGET_ABI_64
#define TARGET_LP64_P(x) TARGET_ABI_64_P(x)
const wide_int_bitmask PTA_AMX_TILE(0, HOST_WIDE_INT_1U << 19);
const wide_int_bitmask PTA_AMX_INT8(0, HOST_WIDE_INT_1U << 20);
const wide_int_bitmask PTA_AMX_BF16(0, HOST_WIDE_INT_1U << 21);
+const wide_int_bitmask PTA_UINTR (0, HOST_WIDE_INT_1U << 22);
const wide_int_bitmask PTA_X86_64_BASELINE = PTA_64BIT | PTA_MMX | PTA_SSE
| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR;
| PTA_MOVBE | PTA_XSAVE;
const wide_int_bitmask PTA_X86_64_V4 = PTA_X86_64_V3
| PTA_AVX512F | PTA_AVX512BW | PTA_AVX512CD | PTA_AVX512DQ | PTA_AVX512VL;
+
const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
| PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
const wide_int_bitmask PTA_SAPPHIRERAPIDS = PTA_COOPERLAKE | PTA_MOVDIRI
| PTA_MOVDIR64B | PTA_AVX512VP2INTERSECT | PTA_ENQCMD | PTA_CLDEMOTE
| PTA_PTWRITE | PTA_WAITPKG | PTA_SERIALIZE | PTA_TSXLDTRK | PTA_AMX_TILE
- | PTA_AMX_INT8 | PTA_AMX_BF16;
+ | PTA_AMX_INT8 | PTA_AMX_BF16 | PTA_UINTR;
const wide_int_bitmask PTA_ALDERLAKE = PTA_SKYLAKE | PTA_CLDEMOTE | PTA_PTWRITE
| PTA_WAITPKG | PTA_SERIALIZE;
const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
UNSPECV_UMONITOR
UNSPECV_TPAUSE
+ ;; For UINTR support
+ UNSPECV_CLUI
+ UNSPECV_STUI
+ UNSPECV_TESTUI
+ UNSPECV_SENDUIPI
+
;; For CLDEMOTE support
UNSPECV_CLDEMOTE
(unspec [(const_int 0)] UNSPEC_INTERRUPT_RETURN)]
"reload_completed"
{
- return TARGET_64BIT ? "iretq" : "iret";
+ return TARGET_64BIT ? (TARGET_UINTR ? "uiret" : "iretq") : "iret";
})
;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
"enqcmd<enqcmd_sfx>\t{%1, %0|%0, %1}"
[(set_attr "type" "other")])
+;; UINTR
+(define_int_iterator UINTR [UNSPECV_CLUI UNSPECV_STUI])
+(define_int_attr uintr [(UNSPECV_CLUI "clui") (UNSPECV_STUI "stui")])
+
+(define_insn "<uintr>"
+ [(unspec_volatile [(const_int 0)] UINTR)]
+ "TARGET_UINTR && TARGET_64BIT"
+ "<uintr>"
+ [(set_attr "type" "other")
+ (set_attr "length" "4")])
+
+(define_insn "testui"
+ [(set (reg:CCC FLAGS_REG)
+ (unspec_volatile:CCC [(const_int 0)] UNSPECV_TESTUI))]
+ "TARGET_UINTR && TARGET_64BIT"
+ "testui"
+ [(set_attr "type" "other")
+ (set_attr "length" "4")])
+
+(define_insn "senduipi"
+ [(unspec_volatile
+ [(match_operand:DI 0 "register_operand" "r")]
+ UNSPECV_SENDUIPI)]
+ "TARGET_UINTR && TARGET_64BIT"
+ "senduipi\t%0"
+ [(set_attr "type" "other")
+ (set_attr "length" "4")])
+
;; WAITPKG
(define_insn "umwait"
Target Report Mask(ISA2_PTWRITE) Var(ix86_isa_flags2) Save
Support PTWRITE built-in functions and code generation.
+muintr
+Target Report Mask(ISA2_UINTR) Var(ix86_isa_flags2) Save
+Support UINTR built-in functions and code generation.
+
msgx
Target Report Mask(ISA2_SGX) Var(ix86_isa_flags2) Save
Support SGX built-in functions and code generation.
--- /dev/null
+/* Copyright (C) 2020 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef _X86GPRINTRIN_H_INCLUDED
+# error "Never use <uintrintrin.h> directly; include <x86gprintrin.h> instead."
+#endif
+
+#ifndef _UINTRNTRIN_H_INCLUDED
+#define _UINTRNTRIN_H_INCLUDED
+
+#ifdef __x86_64__
+
+#ifndef __UINTR__
+#pragma GCC push_options
+#pragma GCC target ("uintr")
+#define __DISABLE_UINTR__
+#endif /* __UINTR__ */
+
+struct __uintr_frame
+{
+ /* The position of the most significant bit set in user-interrupt
+ request register. */
+ unsigned long long uirrv;
+ /* RIP of the interrupted user process. */
+ unsigned long long rip;
+ /* RFLAGS of the interrupted user process. */
+ unsigned long long rflags;
+ /* RSP of the interrupted user process. */
+ unsigned long long rsp;
+};
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_clui (void)
+{
+ __builtin_ia32_clui ();
+}
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_stui (void)
+{
+ __builtin_ia32_stui ();
+}
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_senduipi (unsigned long long __R)
+{
+ __builtin_ia32_senduipi (__R);
+}
+
+extern __inline unsigned char
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_testui (void)
+{
+ return __builtin_ia32_testui ();
+}
+
+#ifdef __DISABLE_UINTR__
+#undef __DISABLE_UINTR__
+#pragma GCC pop_options
+#endif /* __DISABLE_UINTR__ */
+
+#endif
+
+#endif /* _UINTRNTRIN_H_INCLUDED. */
#include <tsxldtrkintrin.h>
+#include <uintrintrin.h>
+
#include <waitpkgintrin.h>
#include <wbnoinvdintrin.h>
@cindex @code{target("amx-bf16")} function attribute, x86
Enable/disable the generation of the AMX-BF16 instructions.
+@item uintr
+@itemx no-uintr
+@cindex @code{target("uintr")} function attribute, x86
+Enable/disable the generation of the UINTR instructions.
+
@item cld
@itemx no-cld
@cindex @code{target("cld")} function attribute, x86
-mvpclmulqdq -mavx512bitalg -mmovdiri -mmovdir64b -mavx512vpopcntdq @gol
-mavx5124fmaps -mavx512vnni -mavx5124vnniw -mprfchw -mrdpid @gol
-mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk@gol
--mamx-tile -mamx-int8 -mamx-bf16@gol
+-mamx-tile -mamx-int8 -mamx-bf16 -muintr@gol
-mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops @gol
-minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol
-mmemcpy-strategy=@var{strategy} -mmemset-strategy=@var{strategy} @gol
@need 200
@itemx -menqcmd
@opindex menqcmd
+@itemx -muintr
+@opindex muintr
@need 200
@itemx -mtsxldtrk
@opindex mtsxldtrk
3DNow!@:, enhanced 3DNow!@:, POPCNT, ABM, ADX, BMI, BMI2, LZCNT, FXSR, XSAVE,
XSAVEOPT, XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, PKU, AVX512VBMI2,
GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16,
-ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE
-or CLDEMOTE extended instruction sets. Each has a corresponding
+ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE,
+UINTR or CLDEMOTE extended instruction sets. Each has a corresponding
@option{-mno-} option to disable use of these instructions.
These extensions are also available as built-in functions: see
extern void test_amx_tile (void) __attribute__((__target__("amx-tile")));
extern void test_amx_int8 (void) __attribute__((__target__("amx-int8")));
extern void test_amx_bf16 (void) __attribute__((__target__("amx-bf16")));
+extern void test_uintr (void) __attribute__((__target__("uintr")));
extern void test_no_sgx (void) __attribute__((__target__("no-sgx")));
extern void test_no_avx5124fmaps(void) __attribute__((__target__("no-avx5124fmaps")));
extern void test_no_amx_tile (void) __attribute__((__target__("no-amx-tile")));
extern void test_no_amx_int8 (void) __attribute__((__target__("no-amx-int8")));
extern void test_no_amx_bf16 (void) __attribute__((__target__("no-amx-bf16")));
+extern void test_no_uintr (void) __attribute__((__target__("no-uintr")));
extern void test_arch_nocona (void) __attribute__((__target__("arch=nocona")));
extern void test_arch_core2 (void) __attribute__((__target__("arch=core2")));
--- /dev/null
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -muintr" } */
+/* { dg-final { scan-assembler-times "clui" "1" } } */
+/* { dg-final { scan-assembler-times "stui" "2" } } */
+/* { dg-final { scan-assembler-times "senduipi" "1" } } */
+/* { dg-final { scan-assembler-times "setc" "1" } } */
+/* { dg-final { scan-assembler-times "testui" "1" } } */
+
+#include <x86gprintrin.h>
+
+extern volatile unsigned char c;
+extern volatile unsigned long long l;
+
+void
+foo (void)
+{
+ _clui ();
+ _stui ();
+ _senduipi (l);
+ c = _testui ();
+}
--- /dev/null
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -muintr -mgeneral-regs-only" } */
+/* { dg-final { scan-assembler-times "uiret" "2" } } */
+
+#include <x86gprintrin.h>
+
+void
+__attribute__((interrupt))
+foo (void *frame)
+{
+}
+
+void
+__attribute__((interrupt))
+UINTR_hanlder (struct __uintr_frame *frame)
+{
+}
--- /dev/null
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -muintr" } */
+/* { dg-final { scan-assembler "uiret" } } */
+#include <x86gprintrin.h>
+
+void __attribute__ ((target("general-regs-only"), interrupt))
+UINTR_handler (struct __uintr_frame *p)
+{
+}
--- /dev/null
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -muintr" } */
+
+#include <x86gprintrin.h>
+
+void __attribute__ ((interrupt))
+UINTR_handler (struct __uintr_frame *p)
+{ /* { dg-message "SSE instructions aren't allowed in an interrupt service routine" } */
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -muintr" } */
+/* { dg-error "'-muintr' not supported for 32-bit code" "" { target ia32 } 0 } */
+
+#include <x86gprintrin.h>
+
+void
+UINTR_hanlder (struct __uintr_frame *frame)
+{
+}
/* Test that <x86gprintrin.h> is usable with -O -std=c89 -pedantic-errors. */
/* { dg-do compile } */
/* { dg-options "-O -std=c89 -pedantic-errors -march=x86-64 -madx -mbmi -mbmi2 -mcldemote -mclflushopt -mclwb -mclzero -menqcmd -mfsgsbase -mfxsr -mlzcnt -mlwp -mmovdiri -mmwaitx -mpconfig -mpopcnt -mpku -mptwrite -mrdpid -mrdrnd -mrdseed -mrtm -mserialize -msgx -mshstk -mtbm -mtsxldtrk -mwaitpkg -mwbnoinvd -mxsave -mxsavec -mxsaveopt -mxsaves -mno-sse -mno-mmx" } */
+/* { dg-additional-options "-muintr" { target { ! ia32 } } } */
#include <x86gprintrin.h>
/* { dg-do compile } */
/* { dg-options "-O2 -Werror-implicit-function-declaration -march=x86-64 -madx -mbmi -mbmi2 -mcldemote -mclflushopt -mclwb -mclzero -menqcmd -mfsgsbase -mfxsr -mlzcnt -mlwp -mmovdiri -mmwaitx -mpconfig -mpopcnt -mpku -mptwrite -mrdpid -mrdrnd -mrdseed -mrtm -mserialize -msgx -mshstk -mtbm -mtsxldtrk -mwaitpkg -mwbnoinvd -mxsave -mxsavec -mxsaveopt -mxsaves -mno-sse -mno-mmx" } */
/* { dg-add-options bind_pic_locally } */
+/* { dg-additional-options "-muintr" { target { ! ia32 } } } */
/* Test that the intrinsics in <x86gprintrin.h> compile with optimization.
All of them are defined as inline functions that reference the proper
/* { dg-do compile } */
/* { dg-options "-O0 -Werror-implicit-function-declaration -march=x86-64 -madx -mbmi -mbmi2 -mcldemote -mclflushopt -mclwb -mclzero -menqcmd -mfsgsbase -mfxsr -mlzcnt -mlwp -mmovdiri -mmwaitx -mpconfig -mpopcnt -mpku -mptwrite -mrdpid -mrdrnd -mrdseed -mrtm -mserialize -msgx -mshstk -mtbm -mtsxldtrk -mwaitpkg -mwbnoinvd -mxsave -mxsavec -mxsaveopt -mxsaves -mno-sse -mno-mmx" } */
/* { dg-add-options bind_pic_locally } */
+/* { dg-additional-options "-muintr" { target { ! ia32 } } } */
/* Test that the intrinsics in <x86gprintrin.h> compile without optimization.
All of them are defined as inline functions that reference the proper
#define __inline
#ifndef DIFFERENT_PRAGMAS
+#ifdef __x86_64__
+#pragma GCC target ("adx,bmi,bmi2,fsgsbase,fxsr,lwp,lzcnt,popcnt,rdrnd,rdseed,tbm,rtm,serialize,tsxldtrk,uintr,xsaveopt")
+#else
#pragma GCC target ("adx,bmi,bmi2,fsgsbase,fxsr,lwp,lzcnt,popcnt,rdrnd,rdseed,tbm,rtm,serialize,tsxldtrk,xsaveopt")
#endif
+#endif
/* popcnintrin.h (POPCNT). */
#ifdef DIFFERENT_PRAGMAS
/* rtmintrin.h */
#define __builtin_ia32_xabort(M) __builtin_ia32_xabort(1)
+#ifdef __x86_64__
+#pragma GCC target ("adx,bmi,bmi2,clflushopt,clwb,clzero,enqcmd,fsgsbase,fxsr,lwp,lzcnt,mwaitx,pconfig,pku,popcnt,rdpid,rdrnd,rdseed,tbm,rtm,serialize,sgx,tsxldtrk,uintr,xsavec,xsaveopt,xsaves,wbnoinvd")
+#else
#pragma GCC target ("adx,bmi,bmi2,clflushopt,clwb,clzero,enqcmd,fsgsbase,fxsr,lwp,lzcnt,mwaitx,pconfig,pku,popcnt,rdpid,rdrnd,rdseed,tbm,rtm,serialize,sgx,tsxldtrk,xsavec,xsaveopt,xsaves,wbnoinvd")
+#endif
#include <x86gprintrin.h>
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