radeonsi: don't flush HTILE if there is no HTILE clear

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index f8136d2b2c4310efd8f5164c92d2d9fd172d2136..4e05d9bf5b27b231d30104fd297b12eded98dc0c 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -593,9 +593,9 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
                 *
                 * This hack decreases back-to-back ClearDepth performance.
                 */
-               if (sctx->screen->clear_db_cache_before_clear) {
+               if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
+                   sctx->screen->clear_db_cache_before_clear)
                        sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
-               }
        }
 
        si_blitter_begin(sctx, SI_CLEAR);