Cleanup synth_xilinx

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index e7fb269e95a39689c626e09edac57be4676359ed..a35b0742bd32060cb6c9237e6293783df4ec1fc4 100644 (file)
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -95,7 +95,7 @@ module \$__SHREG_ (input C, input D, input [31:0] L, input E, output Q);
         MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6]));
       end
     end
-    else if (DEPTH < 129 || (DEPTH <= 129 && &_TECHMAP_CONSTMSK_L_)) begin
+    else if (DEPTH <= 128 || (DEPTH == 129 && &_TECHMAP_CONSTMSK_L_)) begin
       // Handle cases where depth is just 1 over a convenient value,
       if (&_TECHMAP_CONSTMSK_L_) begin
         // For constant length, use the flop

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 443ac4eed6319e44e6489a8334d91a2ba6c6ee9b..763732fe57f836b6507f312b27f2df576cc0c4b6 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -110,6 +110,7 @@ struct SynthXilinxPass : public Pass
                log("        dffsr2dff\n");
                log("        dff2dffe\n");
                log("        opt -full\n");
+               log("        simplemap t:$dff*\n");
                log("        shregmap -tech xilinx\n");
                log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v +/xilinx/ff_map.v\n");
                log("        opt -fast\n");
@@ -257,8 +258,6 @@ struct SynthXilinxPass : public Pass
 
                        Pass::call(design, "simplemap t:$dff*");
                        Pass::call(design, "shregmap -tech xilinx");
-                       Pass::call(design, "techmap -map +/xilinx/cells_map.v t:$__SHREG_");
-                       Pass::call(design, "opt -fast");
 
                        if (vpr) {
                                Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY");