riscv: Convert RISCV to use local reg index storage.

This was mostly straightforward, except that the micro and macro op
classes need to be seperated for AMO classes so that the reg_idx_arr_decl
will have the right sizes.

Change-Id: Ibc0a9df0cb79924342eaceb0f09606913442f841
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36881
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/riscv/isa/formats/amo.isa b/src/arch/riscv/isa/formats/amo.isa
index 7d01145e3cacd3bcdd36779f1d4e982bda2e75c4..cde0fd85a02f428a693a3173fc71644868c7607e 100644 (file)
--- a/src/arch/riscv/isa/formats/amo.isa
+++ b/src/arch/riscv/isa/formats/amo.isa
@@ -38,23 +38,31 @@ def template AtomicMemOpDeclare {{
         // Constructor
         %(class_name)s(ExtMachInst machInst);
 
-    protected:
-
+      protected:
         /*
          * The main RMW part of an AMO
          */
-        class %(class_name)sRMW : public %(base_class)sMicro
-        {
-          public:
-            // Constructor
-            %(class_name)sRMW(ExtMachInst machInst, %(class_name)s *_p);
-
-            Fault execute(ExecContext *, Trace::InstRecord *) const override;
-            Fault initiateAcc(ExecContext *,
-                              Trace::InstRecord *) const override;
-            Fault completeAcc(PacketPtr, ExecContext *,
-                              Trace::InstRecord *) const override;
-        };
+        class %(class_name)sRMW;
+    };
+}};
+
+def template AtomicMemOpRMWDeclare {{
+    /*
+     * The main RMW part of an AMO
+     */
+    class %(class_name)s::%(class_name)sRMW : public %(base_class)s
+    {
+      private:
+        %(reg_idx_arr_decl)s;
+
+      public:
+        // Constructor
+        %(class_name)sRMW(ExtMachInst machInst, %(class_name)s *_p);
+
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 
@@ -68,20 +76,25 @@ def template LRSCDeclare {{
         // Constructor
         %(class_name)s(ExtMachInst machInst);
 
-    protected:
+      protected:
+        class %(class_name)sMicro;
+    };
+}};
+
+def template LRSCMicroDeclare {{
+    class %(class_name)s::%(class_name)sMicro : public %(base_class)s
+    {
+      private:
+        %(reg_idx_arr_decl)s;
 
-        class %(class_name)sMicro : public %(base_class)sMicro
-        {
-          public:
-            // Constructor
-            %(class_name)sMicro(ExtMachInst machInst, %(class_name)s *_p);
+      public:
+        // Constructor
+        %(class_name)sMicro(ExtMachInst machInst, %(class_name)s *_p);
 
-            Fault execute(ExecContext *, Trace::InstRecord *) const override;
-            Fault initiateAcc(ExecContext *,
-                              Trace::InstRecord *) const override;
-            Fault completeAcc(PacketPtr, ExecContext *,
-                              Trace::InstRecord *) const override;
-        };
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 
@@ -141,8 +154,9 @@ def template LRSCMacroConstructor {{
 def template LRSCMicroConstructor {{
     %(class_name)s::%(class_name)sMicro::%(class_name)sMicro(
         ExtMachInst machInst, %(class_name)s *_p)
-            : %(base_class)sMicro("%(mnemonic)s", machInst, %(op_class)s)
+            : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
     {
+        %(set_reg_idx_arr)s;
         %(constructor)s;
     }
 }};
@@ -204,6 +218,7 @@ def template AtomicMemOpRMWConstructor {{
         ExtMachInst machInst, %(class_name)s *_p)
             : %(base_class)s("%(mnemonic)s[l]", machInst, %(op_class)s)
     {
+        %(set_reg_idx_arr)s;
         %(constructor)s;
 
         // overwrite default flags
@@ -472,12 +487,13 @@ def format LoadReserved(memacc_code, postacc_code={{ }}, ea_code={{EA = Rs1;}},
 
     mem_flags = makeList(mem_flags)
     inst_flags = makeList(inst_flags)
-    iop = InstObjParams(name, Name, 'LoadReserved',
+    iop = InstObjParams(name, Name, 'LoadReservedMicro',
         {'ea_code': ea_code, 'memacc_code': memacc_code,
         'postacc_code': postacc_code}, inst_flags)
     iop.constructor += '\n\tmemAccessFlags = memAccessFlags | ' + \
         '|'.join(['Request::%s' % flag for flag in mem_flags]) + ';'
 
+    header_output += LRSCMicroDeclare.subst(iop)
     decoder_output += LRSCMicroConstructor.subst(iop)
     decode_block += BasicDecode.subst(iop)
     exec_output += LoadReservedExecute.subst(iop) \
@@ -499,12 +515,13 @@ def format StoreCond(memacc_code, postacc_code={{ }}, ea_code={{EA = Rs1;}},
 
     mem_flags = makeList(mem_flags)
     inst_flags = makeList(inst_flags)
-    iop = InstObjParams(name, Name, 'StoreCond',
+    iop = InstObjParams(name, Name, 'StoreCondMicro',
         {'ea_code': ea_code, 'memacc_code': memacc_code,
         'postacc_code': postacc_code}, inst_flags)
     iop.constructor += '\n\tmemAccessFlags = memAccessFlags | ' + \
         '|'.join(['Request::%s' % flag for flag in mem_flags]) + ';'
 
+    header_output += LRSCMicroDeclare.subst(iop)
     decoder_output += LRSCMicroConstructor.subst(iop)
     decode_block += BasicDecode.subst(iop)
     exec_output += StoreCondExecute.subst(iop) \
@@ -536,6 +553,7 @@ def format AtomicMemOp(memacc_code, amoop_code, postacc_code={{ }},
     rmw_iop.constructor += '\n\tmemAccessFlags = memAccessFlags | ' + \
           '|'.join(['Request::%s' % flag for flag in rmw_mem_flags]) + ';'
 
+    header_output += AtomicMemOpRMWDeclare.subst(rmw_iop)
     decoder_output += AtomicMemOpRMWConstructor.subst(rmw_iop)
     decode_block += BasicDecode.subst(rmw_iop)
     exec_output += AtomicMemOpRMWExecute.subst(rmw_iop) \

diff --git a/src/arch/riscv/isa/formats/basic.isa b/src/arch/riscv/isa/formats/basic.isa
index 1c597e86b9b6c02365a7bfdefbfb2520b30df4b0..4b9f6c9a13861f89a3b364eab1286c76c2e6d9bc 100644 (file)
--- a/src/arch/riscv/isa/formats/basic.isa
+++ b/src/arch/riscv/isa/formats/basic.isa
@@ -34,6 +34,9 @@ def template BasicDeclare {{
     //
     class %(class_name)s : public %(base_class)s
     {
+      private:
+        %(reg_idx_arr_decl)s;
+
       public:
         /// Constructor.
         %(class_name)s(MachInst machInst);
@@ -47,6 +50,7 @@ def template BasicConstructor {{
     %(class_name)s::%(class_name)s(MachInst machInst)
         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
     {
+        %(set_reg_idx_arr)s;
         %(constructor)s;
     }
 }};

diff --git a/src/arch/riscv/isa/formats/compressed.isa b/src/arch/riscv/isa/formats/compressed.isa
index b9709126f16b556f90140268df346e2348fea6e4..ad733831138b7dea85ca4e42a701f300ffcdd198 100644 (file)
--- a/src/arch/riscv/isa/formats/compressed.isa
+++ b/src/arch/riscv/isa/formats/compressed.isa
@@ -120,6 +120,9 @@ def template CBasicDeclare {{
     //
     class %(class_name)s : public %(base_class)s
     {
+      private:
+        %(reg_idx_arr_decl)s;
+
       public:
         /// Constructor.
         %(class_name)s(MachInst machInst);

diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa
index faaae6f772620480987e219c5fda0de81879758d..1dd9dc262ba5b6016184e8dee1090cc0969991af 100644 (file)
--- a/src/arch/riscv/isa/formats/mem.isa
+++ b/src/arch/riscv/isa/formats/mem.isa
@@ -37,6 +37,9 @@ def template LoadStoreDeclare {{
      */
     class %(class_name)s : public %(base_class)s
     {
+      private:
+        %(reg_idx_arr_decl)s;
+
       public:
         /// Constructor.
         %(class_name)s(ExtMachInst machInst);
@@ -53,6 +56,7 @@ def template LoadStoreConstructor {{
     %(class_name)s::%(class_name)s(ExtMachInst machInst):
         %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
     {
+        %(set_reg_idx_arr)s;
         %(constructor)s;
         %(offset_code)s;
     }

diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa
index 04a469f83d9837ae581e95912bb78d77c1945a3e..72f7dc1d29c0bf0381a3946dda22fda54d8d177c 100644 (file)
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -39,6 +39,9 @@ def template ImmDeclare {{
     //
     class %(class_name)s : public %(base_class)s
     {
+      private:
+        %(reg_idx_arr_decl)s;
+
       public:
         /// Constructor.
         %(class_name)s(MachInst machInst);
@@ -52,6 +55,7 @@ def template ImmConstructor {{
     %(class_name)s::%(class_name)s(MachInst machInst)
         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
     {
+        %(set_reg_idx_arr)s;
         %(constructor)s;
         %(imm_code)s;
     }
@@ -177,6 +181,9 @@ def template BranchDeclare {{
     //
     class %(class_name)s : public %(base_class)s
     {
+      private:
+        %(reg_idx_arr_decl)s;
+
       public:
         /// Constructor.
         %(class_name)s(MachInst machInst);
@@ -237,6 +244,9 @@ def template JumpDeclare {{
     //
     class %(class_name)s : public %(base_class)s
     {
+      private:
+        %(reg_idx_arr_decl)s;
+
       public:
         /// Constructor.
         %(class_name)s(MachInst machInst);