soc: add add_csr_bridge method

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 57c8738a1b74f36d2eb030cb1b17f2b690091ddc..883fec94252c60b8d43af2cb5160399c875e2353 100755 (executable)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -11,8 +11,11 @@ from migen import *
 
 from litex.soc.cores.identifier import Identifier
 from litex.soc.cores.timer import Timer
+
 from litex.soc.interconnect.csr import *
+from litex.soc.interconnect import csr_bus
 from litex.soc.interconnect import wishbone
+from litex.soc.interconnect import wishbone2csr
 
 # TODO:
 # - replace raise with exit on logging error.
@@ -378,6 +381,11 @@ class SoCCSRHandler(SoCLocHandler):
                 colorer(alignment, color="red"),
                 colorer(", ".join(str(x) for x in self.supported_alignment), color="green")))
             raise
+        if data_width > alignment:
+            self.logger.error("Alignment ({}) should be >= data_width ({})".format(
+                colorer(alignment,  color="red"),
+                colorer(data_width, color="red")))
+            raise
 
         # Check Paging
         if paging not in self.supported_paging:
@@ -578,6 +586,14 @@ class SoC(Module):
         self.csr.add(name, use_loc_if_exists=True)
         self.irq.add(name, use_loc_if_exists=True)
 
+    def add_csr_bridge(self, origin):
+        self.submodules.csr_bridge = wishbone2csr.WB2CSR(
+            bus_csr       = csr_bus.Interface(
+            address_width = self.csr.address_width,
+            data_width    = self.csr.data_width))
+        csr_size = 2**(self.csr.address_width + 2)
+        self.bus.add_slave("csr", self.csr_bridge.wishbone, SoCRegion(origin=origin, size=csr_size))
+
     # SoC finalization -----------------------------------------------------------------------------
     def do_finalize(self):
         self.logger.info(colorer("-"*80, color="bright"))

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 68d2e29b6699f6971ccd178dfb8e609819de326b..8d6398ecc81d29f5a49c3b2ce55307fd4639cfe1 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -123,6 +123,7 @@ class SoCCore(SoC):
 
         self.csr_data_width             = csr_data_width
         self.csr_address_width          = csr_address_width
+        self.csr_alignment              = csr_alignment
 
         self.with_wishbone              = with_wishbone
         self.wishbone_timeout_cycles    = wishbone_timeout_cycles
@@ -232,16 +233,9 @@ class SoCCore(SoC):
         # Add Wishbone to CSR bridge
         self.config["CSR_DATA_WIDTH"] = csr_data_width
         self.config["CSR_ALIGNMENT"]  = csr_alignment
-        assert csr_data_width <= csr_alignment
-        self.csr_data_width = csr_data_width
-        self.csr_alignment  = csr_alignment
         if with_wishbone:
-            self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
-                bus_csr=csr_bus.Interface(
-                    address_width = csr_address_width,
-                    data_width    = csr_data_width))
-            self.add_csr_master(self.wishbone2csr.csr)
-            self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 2**(csr_address_width + 2))
+            self.add_csr_bridge(self.soc_mem_map["csr"])
+            self.add_csr_master(self.csr_bridge.csr) # FIXME
 
     # Methods --------------------------------------------------------------------------------------