--- /dev/null
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+type=MinorOpClassSet
+children=opClasses0 opClasses1
+eventq_index=0
+opClasses=system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses1
+
+[system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses0]
+type=MinorOpClass
+eventq_index=0
+opClass=IprAccess
+
+[system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses1]
+type=MinorOpClass
+eventq_index=0
+opClass=InstPrefetch
+
+[system.cpu1.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=1
+is_top_level=true
+max_miss_count=0
+mshrs=2
+prefetch_on_access=false
+prefetcher=Null
+response_latency=1
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu1.icache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.icache_port
+mem_side=system.cpu1.toL2Bus.slave[0]
+
+[system.cpu1.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=1
+sequential_access=false
+size=32768
+
+[system.cpu1.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu1.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu1.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+tlb=system.cpu1.itb
+
+[system.cpu1.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu1.istage2_mmu.stage2_tlb.walker
+
+[system.cpu1.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu1.toL2Bus.slave[4]
+
+[system.cpu1.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu1.toL2Bus.slave[2]
+
+[system.cpu1.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu1.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu1.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu1.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu1.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu1.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu1.l2cache.cpu_side
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+
+[system.cpu1.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+use_default_range=true
+width=8
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
+eventq_index=0
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.l2c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.l2c.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=2147483648:2415919103
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
+tWTR=7500
+tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.l2c.cpu_side
+slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 09:18:22
+gem5 started Oct 29 2014 10:35:48
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu0.isa: ISA system set to: 0x5394b00 0x5394b00
+ 0: system.cpu1.isa: ISA system set to: 0x5394b00 0x5394b00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80080000
+info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 47349475204500 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 47.349475 # Number of seconds simulated
+sim_ticks 47349475204500 # Number of ticks simulated
+final_tick 47349475204500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 170024 # Simulator instruction rate (inst/s)
+host_op_rate 200007 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9521770968 # Simulator tick rate (ticks/s)
+host_mem_usage 827688 # Number of bytes of host memory used
+host_seconds 4972.76 # Real time elapsed on the host
+sim_insts 845490438 # Number of instructions simulated
+sim_ops 994586036 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::realview.ide 457024 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 242432 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 409152 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 13269720 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 28432512 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 254656 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 419648 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 10291040 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 23441792 # Number of bytes read from this memory
+system.physmem.bytes_read::total 77217976 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 3825664 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 566400 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 4392064 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 33722560 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.inst 56250828 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.inst 43534148 # Number of bytes written to this memory
+system.physmem.bytes_written::total 140338128 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 7141 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 3788 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 6393 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 207361 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 444258 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 3979 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 6557 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 160812 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 366278 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1206567 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 526915 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.inst 881196 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.inst 680222 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 2195061 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 9652 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 5120 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 8641 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 280251 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 600482 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 5378 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 8863 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 217342 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 495080 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1630810 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 80796 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 11962 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 92758 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 712206 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 144259 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.inst 1187993 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.inst 919422 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2963879 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 712206 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 153911 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 5120 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 8641 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 1468243 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 600482 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 5378 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 8863 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 1136764 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 495080 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4594689 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1206567 # Number of read requests accepted
+system.physmem.writeReqs 2195061 # Number of write requests accepted
+system.physmem.readBursts 1206567 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 2195061 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 76928704 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 291584 # Total number of bytes read from write queue
+system.physmem.bytesWritten 135133184 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 77217976 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 140338128 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 4556 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 83588 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 93227 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 68916 # Per bank write bursts
+system.physmem.perBankRdBursts::1 78372 # Per bank write bursts
+system.physmem.perBankRdBursts::2 66961 # Per bank write bursts
+system.physmem.perBankRdBursts::3 74483 # Per bank write bursts
+system.physmem.perBankRdBursts::4 67860 # Per bank write bursts
+system.physmem.perBankRdBursts::5 84994 # Per bank write bursts
+system.physmem.perBankRdBursts::6 78873 # Per bank write bursts
+system.physmem.perBankRdBursts::7 74831 # Per bank write bursts
+system.physmem.perBankRdBursts::8 70689 # Per bank write bursts
+system.physmem.perBankRdBursts::9 121049 # Per bank write bursts
+system.physmem.perBankRdBursts::10 55712 # Per bank write bursts
+system.physmem.perBankRdBursts::11 71204 # Per bank write bursts
+system.physmem.perBankRdBursts::12 68805 # Per bank write bursts
+system.physmem.perBankRdBursts::13 80552 # Per bank write bursts
+system.physmem.perBankRdBursts::14 71313 # Per bank write bursts
+system.physmem.perBankRdBursts::15 67397 # Per bank write bursts
+system.physmem.perBankWrBursts::0 131295 # Per bank write bursts
+system.physmem.perBankWrBursts::1 120115 # Per bank write bursts
+system.physmem.perBankWrBursts::2 136218 # Per bank write bursts
+system.physmem.perBankWrBursts::3 122111 # Per bank write bursts
+system.physmem.perBankWrBursts::4 136290 # Per bank write bursts
+system.physmem.perBankWrBursts::5 134780 # Per bank write bursts
+system.physmem.perBankWrBursts::6 183921 # Per bank write bursts
+system.physmem.perBankWrBursts::7 113990 # Per bank write bursts
+system.physmem.perBankWrBursts::8 112648 # Per bank write bursts
+system.physmem.perBankWrBursts::9 120303 # Per bank write bursts
+system.physmem.perBankWrBursts::10 105255 # Per bank write bursts
+system.physmem.perBankWrBursts::11 150368 # Per bank write bursts
+system.physmem.perBankWrBursts::12 133266 # Per bank write bursts
+system.physmem.perBankWrBursts::13 132701 # Per bank write bursts
+system.physmem.perBankWrBursts::14 112511 # Per bank write bursts
+system.physmem.perBankWrBursts::15 165684 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
+system.physmem.totGap 47349473266500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 37 # Read request sizes (log2)
+system.physmem.readPktSize::4 5 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 1206525 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 2 # Write request sizes (log2)
+system.physmem.writePktSize::3 2601 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 2192458 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 701586 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 159041 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 78388 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 62534 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 48409 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 42357 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 36825 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 30566 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 24739 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 6356 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 3319 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 2365 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1772 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1348 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 953 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 724 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 286 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 212 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 134 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 92 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::16 97715 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::27 115005 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 123737 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 112481 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 110136 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 106316 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::34 4456 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::36 2946 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 2503 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 2161 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 1740 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 1473 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 1128 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 896 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 630 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::45 456 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 392 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 367 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 336 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 298 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 248 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 237 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 208 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 184 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 156 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 130 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 66 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 691339 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 306.739519 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 163.472793 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 357.323128 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 329714 47.69% 47.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 128094 18.53% 66.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 46159 6.68% 72.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 24419 3.53% 76.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 20272 2.93% 79.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 13585 1.97% 81.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 10457 1.51% 82.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 11430 1.65% 84.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 107209 15.51% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 691339 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 99075 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 12.132152 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 222.564559 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 99072 100.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::28672-30719 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 99075 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 99075 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 21.311693 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 20.731664 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 6.258880 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 33791 34.11% 34.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 48957 49.41% 83.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 10331 10.43% 93.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 2038 2.06% 96.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 1546 1.56% 97.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 746 0.75% 98.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 511 0.52% 98.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 316 0.32% 99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 116 0.12% 99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 38 0.04% 99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 31 0.03% 99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 20 0.02% 99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 438 0.44% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 35 0.04% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 39 0.04% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 38 0.04% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 24 0.02% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 3 0.00% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 2 0.00% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 1 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 10 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 7 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 4 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 3 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 3 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 17 0.02% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 3 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 4 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 99075 # Writes before turning the bus around for reads
+system.physmem.totQLat 32464480274 # Total ticks spent queuing
+system.physmem.totMemAccLat 55002186524 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 6010055000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 27008.47 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 45758.47 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.62 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.63 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.96 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.40 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 23.37 # Average write queue length when enqueuing
+system.physmem.readRowHits 944165 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1677959 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 78.55 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 79.47 # Row buffer hit rate for writes
+system.physmem.avgGap 13919650.61 # Average gap between requests
+system.physmem.pageHitRate 79.13 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 45391806829500 # Time in different power states
+system.physmem.memoryStateTime::REF 1581102900000 # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem.memoryStateTime::ACT 376561525500 # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem.actEnergy::0 2682083880 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 2544438960 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 1463438625 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 1388334750 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 4643184000 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 4732392600 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 6990105600 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 6692129280 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 3092637272400 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 3092637272400 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 1220178523320 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 1215644323230 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 27339350706750 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 27343328075250 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 31667945314575 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 31666966966470 # Total energy per rank (pJ)
+system.physmem.averagePower::0 668.813072 # Core power per rank (mW)
+system.physmem.averagePower::1 668.792410 # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu0.inst 740 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 584 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 16 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 16 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 16 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 1114990 # Transaction distribution
+system.membus.trans_dist::ReadResp 1114990 # Transaction distribution
+system.membus.trans_dist::WriteReq 37937 # Transaction distribution
+system.membus.trans_dist::WriteResp 37937 # Transaction distribution
+system.membus.trans_dist::Writeback 526915 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 1665543 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 1665543 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 343558 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 290459 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 93233 # Transaction distribution
+system.membus.trans_dist::ReadExReq 145423 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131308 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122918 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 23584 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6789962 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 6936516 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229526 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 229526 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 7166042 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156048 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 47168 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210268488 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 210473028 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7287616 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7287616 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 217760644 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 556693 # Total snoops (count)
+system.membus.snoop_fanout::samples 3996553 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3996553 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 3996553 # Request fanout histogram
+system.membus.reqLayer0.occupancy 106711482 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 35984 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 20060995 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 21791270978 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 13392760110 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer3.occupancy 187374753 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.l2c.tags.replacements 893379 # number of replacements
+system.l2c.tags.tagsinuse 64139.353797 # Cycle average of tags in use
+system.l2c.tags.total_refs 6866398 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 953433 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 7.201762 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 10411.534254 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker 170.665758 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker 236.653363 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 5522.014615 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 25703.497535 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker 145.004713 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker 188.005532 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 6322.307070 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 15439.670958 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.158867 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002604 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker 0.003611 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst 0.084259 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.392204 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002213 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker 0.002869 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.096471 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.235591 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.978689 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022 36012 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023 260 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024 23782 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1 41 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2 716 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3 1957 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4 33290 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::1 7 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3 51 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4 190 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 1450 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3 3907 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4 18298 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022 0.549500 # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id
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+system.l2c.overall_mshr_hits::total 470 # number of overall MSHR hits
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+system.l2c.UpgradeReq_mshr_misses::cpu1.inst 34601 # number of UpgradeReq MSHR misses
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+system.l2c.overall_mshr_misses::total 1151046 # number of overall MSHR misses
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+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 6471220731 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 33572512037 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 87083288091 # number of ReadReq MSHR miss cycles
+system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 17889181875 # number of WriteInvalidateReq MSHR miss cycles
+system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 13903512484 # number of WriteInvalidateReq MSHR miss cycles
+system.l2c.WriteInvalidateReq_mshr_miss_latency::total 31792694359 # number of WriteInvalidateReq MSHR miss cycles
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 351692080 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 724460670 # number of UpgradeReq MSHR miss cycles
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+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 86940850 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 183636150 # number of SCUpgradeReq MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 262923496 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 430600242 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 10431954111 # number of demand (read+write) MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 428022244 # number of overall MSHR miss cycles
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4946669501 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3170681000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 8117350501 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 2118382500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 3125324001 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 5243706501 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 7065052001 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6296005001 # number of overall MSHR uncacheable cycles
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+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.348867 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.588728 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.135708 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.179259 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.352217 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.588758 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.156753 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.162974 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.168353 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.548886 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.559479 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.553982 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.563932 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.544385 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.554511 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.575379 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.558051 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.566838 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.348867 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.588728 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.205233 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.179259 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.352217 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.588758 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.220873 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.162974 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.183522 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.348867 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.588728 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.205233 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.179259 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.352217 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.588758 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.220873 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.162974 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.183522 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 66737.669399 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66717.054807 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 85735.610037 # average ReadReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst inf # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst inf # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10179.371655 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10164.217219 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10172.009239 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10202.078498 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10213.915648 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10207.679266 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 60979.791401 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60315.430582 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 60657.412408 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64185.061821 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64132.705309 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 82787.198548 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64185.061821 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64132.705309 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 82787.198548 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq 6929805 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 6922247 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 37937 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 37937 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 1844732 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 1665553 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 1558815 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 396880 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 304912 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 701792 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 122 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 286652 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 286652 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10302950 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9169444 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 19472394 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 332778181 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 290120831 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 622899012 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 1503135 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 11338555 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.010201 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.100485 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 11222888 98.98% 98.98% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 115667 1.02% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 11338555 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 19325316227 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 6157500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 17505808152 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 16090621161 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 40386 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40386 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136543 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136730 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 187 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48036 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122918 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 354232 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48056 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 156048 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7497086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36503000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 982100345 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 92919000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 179226247 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.cpu0.branchPred.lookups 130284886 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 91971902 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 5996877 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 97983342 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 71203631 # Number of BTB hits
+system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu0.branchPred.BTBHitPct 72.669119 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 15456951 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 1030979 # Number of incorrect RAS predictions.
+system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 84560824 # DTB read hits
+system.cpu0.dtb.read_misses 213472 # DTB read misses
+system.cpu0.dtb.write_hits 73762718 # DTB write hits
+system.cpu0.dtb.write_misses 44801 # DTB write misses
+system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 35801 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1794 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 7921 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 10648 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 84774296 # DTB read accesses
+system.cpu0.dtb.write_accesses 73807519 # DTB write accesses
+system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dtb.hits 158323542 # DTB hits
+system.cpu0.dtb.misses 258273 # DTB misses
+system.cpu0.dtb.accesses 158581815 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.inst_hits 233888906 # ITB inst hits
+system.cpu0.itb.inst_misses 61464 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 25786 # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults 208811 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.inst_accesses 233950370 # ITB inst accesses
+system.cpu0.itb.hits 233888906 # DTB hits
+system.cpu0.itb.misses 61464 # DTB misses
+system.cpu0.itb.accesses 233950370 # DTB accesses
+system.cpu0.numCycles 883850249 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.committedInsts 434327088 # Number of instructions committed
+system.cpu0.committedOps 509859279 # Number of ops (including micro ops) committed
+system.cpu0.discardedOps 43671037 # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends 5040 # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles 93815840018 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi 2.034988 # CPI: cycles per instruction
+system.cpu0.ipc 0.491403 # IPC: instructions per cycle
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 5406 # number of quiesce instructions executed
+system.cpu0.tickCycles 675499590 # Number of cycles that the object actually ticked
+system.cpu0.idleCycles 208350659 # Total number of cycles that the object has spent stopped
+system.cpu0.icache.tags.replacements 9024677 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.937426 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 224649292 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 9025189 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 24.891367 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 16724996500 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.937426 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999878 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.999878 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses 476374153 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 476374153 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 224649292 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 224649292 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 224649292 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 224649292 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 224649292 # number of overall hits
+system.cpu0.icache.overall_hits::total 224649292 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 9025190 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 9025190 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 9025190 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 9025190 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 9025190 # number of overall misses
+system.cpu0.icache.overall_misses::total 9025190 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 76329373412 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 76329373412 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 76329373412 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 76329373412 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 76329373412 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 76329373412 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 233674482 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 233674482 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 233674482 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 233674482 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 233674482 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 233674482 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038623 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.038623 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038623 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.038623 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038623 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.038623 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8457.370251 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 8457.370251 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8457.370251 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 8457.370251 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8457.370251 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 8457.370251 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9025190 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 9025190 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 9025190 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 9025190 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 9025190 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 9025190 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 62781832574 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 62781832574 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 62781832574 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 62781832574 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 62781832574 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 62781832574 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4713380500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4713380500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4713380500 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total 4713380500 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038623 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038623 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038623 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.038623 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038623 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.038623 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6956.289294 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6956.289294 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6956.289294 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 6956.289294 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6956.289294 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 6956.289294 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.toL2Bus.trans_dist::ReadReq 16744363 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 13538941 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 16377 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 16377 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 2993146 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 4286145 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1665553 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 878594 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 389729 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 340122 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 446153 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1234377 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1099479 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18154960 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15139641 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 334891 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1016427 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 34645919 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 580958656 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 555417413 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1211560 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3676024 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 1141263653 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 9180766 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 27586114 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 5.321691 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.467125 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5 18711910 67.83% 67.83% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6 8874204 32.17% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 27586114 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 13279117937 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 196246989 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer0.occupancy 13633302169 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer1.occupancy 7744080967 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer2.occupancy 184135419 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer3.occupancy 557460915 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 80006652 # number of hwpf identified
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 1538976 # number of hwpf that were already in mshr
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 75387543 # number of hwpf that were already in the cache
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49644 # number of hwpf that were already in the prefetch queue
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2517 # number of hwpf removed because MSHR allocated
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 3027964 # number of hwpf issued
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 6795468 # number of hwpf spanning a virtual page
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu0.l2cache.tags.replacements 3295318 # number of replacements
+system.cpu0.l2cache.tags.tagsinuse 16239.521092 # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs 15183735 # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs 3311433 # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs 4.585246 # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle 14515776000 # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks 5108.942549 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 64.019654 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 70.169979 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2735.324727 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8261.064181 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks 0.311825 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003907 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004283 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.166951 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.504215 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total 0.991182 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022 10731 # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024 5301 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 116 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 730 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2564 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4307 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 3014 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 30 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 447 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1426 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2059 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1321 # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.654968 # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.323547 # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses 302494843 # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses 302494843 # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 445653 # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140462 # number of ReadReq hits
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+system.cpu0.l2cache.ReadReq_hits::total 12304073 # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks 2993146 # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total 2993146 # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 70651 # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total 70651 # number of UpgradeReq hits
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+system.cpu0.l2cache.SCUpgradeReq_hits::total 35155 # number of SCUpgradeReq hits
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+system.cpu0.l2cache.Writeback_accesses::total 2993146 # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 188213 # number of UpgradeReq accesses(hits+misses)
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+system.cpu0.l2cache.SCUpgradeReq_accesses::total 188544 # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu0.l2cache.overall_accesses::cpu0.inst 13722710 # number of overall (read+write) accesses
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+system.cpu0.dcache.tags.sampled_refs 5337832 # Sample count of references to valid blocks.
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+system.cpu0.dcache.StoreCondReq_miss_latency::total 3978646923 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 2553000 # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2553000 # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.inst 89631520887 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 89631520887 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.inst 89631520887 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 89631520887 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.inst 81622791 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 81622791 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.inst 70704654 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 70704654 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst 878594 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::total 878594 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 1861437 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 1861437 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 1860095 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 1860095 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.inst 152327445 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 152327445 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.inst 152327445 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 152327445 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.047233 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.047233 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030840 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.030840 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.062703 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062703 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.101393 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.101393 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.039624 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.039624 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.039624 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.039624 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 13734.123410 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13734.123410 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 16822.796313 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 16822.796313 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 13559.980594 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13559.980594 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21095.688881 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21095.688881 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 14849.942557 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14849.942557 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 14849.942557 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 14849.942557 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes 878594 # number of fast writes performed
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks 2993146 # number of writebacks
+system.cpu0.dcache.writebacks::total 2993146 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 365860 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 365860 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 900170 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 900170 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 65 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 65 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst 53 # number of StoreCondReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::total 53 # number of StoreCondReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.inst 1266030 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 1266030 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.inst 1266030 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 1266030 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 3489447 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 3489447 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 1279618 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 1279618 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 116652 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 116652 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 188547 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 188547 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.inst 4769065 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 4769065 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.inst 4769065 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 4769065 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 40912958493 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40912958493 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 19695838269 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 19695838269 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 39725259601 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 39725259601 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 1347811737 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1347811737 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 3591126546 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3591126546 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 2234500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2234500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 60608796762 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 60608796762 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 60608796762 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 60608796762 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2590105703 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2590105703 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 2521930197 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2521930197 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 5112035900 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5112035900 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.042751 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.042751 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.018098 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018098 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.062668 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062668 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.101364 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101364 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031308 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.031308 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031308 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.031308 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11724.768564 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11724.768564 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 15391.967188 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15391.967188 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst inf # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 11554.124550 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11554.124550 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19046.320260 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19046.320260 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 12708.737826 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12708.737826 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 12708.737826 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12708.737826 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.branchPred.lookups 124419206 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 87805046 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 6051921 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 92935126 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 66733716 # Number of BTB hits
+system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu1.branchPred.BTBHitPct 71.806774 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 14888837 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 1052333 # Number of incorrect RAS predictions.
+system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.inst_hits 0 # ITB inst hits
+system.cpu1.dtb.inst_misses 0 # ITB inst misses
+system.cpu1.dtb.read_hits 80858392 # DTB read hits
+system.cpu1.dtb.read_misses 227532 # DTB read misses
+system.cpu1.dtb.write_hits 71539111 # DTB write hits
+system.cpu1.dtb.write_misses 46368 # DTB write misses
+system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 35324 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 1220 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 8196 # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults 10514 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 81085924 # DTB read accesses
+system.cpu1.dtb.write_accesses 71585479 # DTB write accesses
+system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dtb.hits 152397503 # DTB hits
+system.cpu1.dtb.misses 273900 # DTB misses
+system.cpu1.dtb.accesses 152671403 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.inst_hits 221287255 # ITB inst hits
+system.cpu1.itb.inst_misses 68040 # ITB inst misses
+system.cpu1.itb.read_hits 0 # DTB read hits
+system.cpu1.itb.read_misses 0 # DTB read misses
+system.cpu1.itb.write_hits 0 # DTB write hits
+system.cpu1.itb.write_misses 0 # DTB write misses
+system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 25097 # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults 202601 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses 0 # DTB read accesses
+system.cpu1.itb.write_accesses 0 # DTB write accesses
+system.cpu1.itb.inst_accesses 221355295 # ITB inst accesses
+system.cpu1.itb.hits 221287255 # DTB hits
+system.cpu1.itb.misses 68040 # DTB misses
+system.cpu1.itb.accesses 221355295 # DTB accesses
+system.cpu1.numCycles 841372178 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.committedInsts 411163350 # Number of instructions committed
+system.cpu1.committedOps 484726757 # Number of ops (including micro ops) committed
+system.cpu1.discardedOps 42974941 # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends 4643 # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles 93858235376 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi 2.046321 # CPI: cycles per instruction
+system.cpu1.ipc 0.488682 # IPC: instructions per cycle
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 13250 # number of quiesce instructions executed
+system.cpu1.tickCycles 646022417 # Number of cycles that the object actually ticked
+system.cpu1.idleCycles 195349761 # Total number of cycles that the object has spent stopped
+system.cpu1.icache.tags.replacements 9199343 # number of replacements
+system.cpu1.icache.tags.tagsinuse 507.111645 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 211878543 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 9199855 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 23.030639 # Average number of references to valid blocks.
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+system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.111645 # Average occupied blocks per requestor
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+system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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+system.cpu1.icache.demand_accesses::cpu1.inst 221078407 # number of demand (read+write) accesses
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+system.cpu1.icache.overall_accesses::total 221078407 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.041614 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.041614 # miss rate for ReadReq accesses
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+system.cpu1.icache.overall_miss_rate::total 0.041614 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8454.521699 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 8454.521699 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8454.521699 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 8454.521699 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8454.521699 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 8454.521699 # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes 0 # number of fast writes performed
+system.cpu1.icache.cache_copies 0 # number of cache copies performed
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9199864 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 9199864 # number of ReadReq MSHR misses
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+system.cpu1.icache.overall_mshr_misses::total 9199864 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 63970402202 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 63970402202 # number of ReadReq MSHR miss cycles
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+system.cpu1.icache.demand_mshr_miss_latency::total 63970402202 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 63970402202 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 63970402202 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8551999 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8551999 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8551999 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total 8551999 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.041614 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.041614 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.041614 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.041614 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.041614 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.041614 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6953.407377 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6953.407377 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6953.407377 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 6953.407377 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6953.407377 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 6953.407377 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.toL2Bus.trans_dist::ReadReq 16974832 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 13523495 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 21560 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 21560 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 2756922 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 3912463 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1665553 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 680221 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 382477 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337171 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 432582 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1151878 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1012928 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18399906 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13962178 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 374507 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1077414 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 33814005 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 588796992 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 509690879 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1369000 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3931224 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 1103788095 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 9217690 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 27159033 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 5.328913 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.469818 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5 18226076 67.11% 67.11% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6 8932957 32.89% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 27159033 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 12584209028 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 175099992 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer0.occupancy 13805070808 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer1.occupancy 7247611234 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer2.occupancy 204139691 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer3.occupancy 586587181 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 79358164 # number of hwpf identified
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 1355061 # number of hwpf that were already in mshr
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 75203006 # number of hwpf that were already in the cache
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49096 # number of hwpf that were already in the prefetch queue
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 3073 # number of hwpf removed because MSHR allocated
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2747928 # number of hwpf issued
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 6733876 # number of hwpf spanning a virtual page
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu1.l2cache.tags.replacements 3063828 # number of replacements
+system.cpu1.l2cache.tags.tagsinuse 13784.638052 # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs 15005563 # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs 3079680 # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs 4.872442 # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle 9994842368500 # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 2928.842366 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.432287 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 61.914602 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2764.974382 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7961.474415 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks 0.178762 # Average percentage of cache occupancy
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+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003779 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.168761 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.485930 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total 0.841348 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9851 # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023 102 # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5899 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 232 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4639 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 3547 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1433 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 75 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2951 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2204 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 483 # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.601257 # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006226 # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.360046 # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses 294450591 # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses 294450591 # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 477253 # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 159835 # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.inst 11727223 # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total 12364311 # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks 2756922 # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total 2756922 # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 68490 # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total 68490 # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 32200 # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total 32200 # number of SCUpgradeReq hits
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+system.cpu1.l2cache.ReadExReq_hits::total 776956 # number of ReadExReq hits
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+system.cpu1.l2cache.demand_hits::cpu1.inst 12504179 # number of demand (read+write) hits
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+system.cpu1.l2cache.overall_hits::total 13141267 # number of overall hits
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+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11290 # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.inst 893170 # number of ReadReq misses
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+system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 118620 # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total 118620 # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 151637 # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total 151637 # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 5 # number of SCUpgradeFailReq misses
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+system.cpu1.l2cache.ReadExReq_misses::total 230937 # number of ReadExReq misses
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+system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11290 # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst 1124107 # number of overall misses
+system.cpu1.l2cache.overall_misses::total 1149547 # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 593312131 # number of ReadReq miss cycles
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+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 26528840524 # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total 27831254828 # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 2374329628 # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total 2374329628 # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 3078262421 # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3078262421 # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 2493000 # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2493000 # number of SCUpgradeFailReq miss cycles
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+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dcache.tags.replacements 4834403 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 460.748614 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 144950857 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 4834915 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 29.980022 # Average number of references to valid blocks.
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+system.cpu1.dcache.ReadReq_miss_latency::total 51111445827 # number of ReadReq miss cycles
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+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13712.378653 # average LoadLockedReq miss latency
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+system.cpu1.dcache.cache_copies 0 # number of cache copies performed
+system.cpu1.dcache.writebacks::writebacks 2756922 # number of writebacks
+system.cpu1.dcache.writebacks::total 2756922 # number of writebacks
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+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042369 # mshr miss rate for ReadReq accesses
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+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12053.939065 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 15716.117120 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15716.117120 # average WriteReq mshr miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11706.242754 # average LoadLockedReq mshr miss latency
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+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19127.283901 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency
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+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13026.102218 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 13026.102218 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13026.102218 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
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+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.tags.replacements 115612 # number of replacements
+system.iocache.tags.tagsinuse 11.299913 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
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+system.iocache.tags.occ_percent::total 0.706245 # Average percentage of cache occupancy
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+system.iocache.overall_accesses::realview.ide 8889 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8929 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
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+system.iocache.WriteInvalidateReq_miss_rate::total 0.001749 # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154081.081081 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 221066.414332 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 220788.747143 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 151450 # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 221066.414332 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 220754.547766 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 151450 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 221066.414332 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 220754.547766 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 54362 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 9.902004 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 106728 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide 8889 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 8926 # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 8889 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 8929 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide 8889 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 8929 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3777000 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 1502702365 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 1506479365 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6627847227 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6627847227 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet 3978000 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 1502702365 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 1506680365 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet 3978000 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 1502702365 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 1506680365 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102081.081081 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 169051.902914 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 168774.295877 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99450 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 169051.902914 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 168740.101355 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99450 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 169051.902914 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 168740.101355 # average overall mshr miss latency
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
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+
+[system.bridge]
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+
+[system.cf0]
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+
+[system.cf0.image]
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+
+[system.cf0.image.child]
+type=RawDiskImage
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+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
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+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
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+branchPred=system.cpu.branchPred
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+decodeCycleInput=true
+decodeInputBufferSize=3
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+decodeToExecuteForwardDelay=1
+do_checkpoint_insts=true
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+interrupts=system.cpu.interrupts
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+simpoint_start_insts=
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+switched_out=false
+system=system
+tracer=system.cpu.tracer
+workload=
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.branchPred]
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+BTBEntries=4096
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+choiceCtrBits=2
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+instShiftAmt=2
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+localHistoryTableSize=2048
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+predType=tournament
+
+[system.cpu.dcache]
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+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
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+
+[system.cpu.dstage2_mmu]
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+
+[system.cpu.dstage2_mmu.stage2_tlb]
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+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
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+num_squash_per_cycle=2
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+
+[system.cpu.dtb]
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+
+[system.cpu.dtb.walker]
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+
+[system.cpu.executeFuncUnits]
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+
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+
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+eventq_index=0
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+
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+
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+
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+
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+
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
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+
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+
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+
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+
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
+type=MinorOpClass
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
+type=MinorOpClass
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
+type=MinorOpClass
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
+type=MinorOpClass
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
+type=MinorOpClass
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
+type=MinorOpClass
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+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
+type=MinorOpClass
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+
+[system.cpu.executeFuncUnits.funcUnits4.timings]
+type=MinorFUTiming
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+srcRegsRelativeLats=2
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
+type=MinorOpClassSet
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+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits5]
+type=MinorFU
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+cantForwardFromFUIndices=
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+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
+opLat=1
+timings=system.cpu.executeFuncUnits.funcUnits5.timings
+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses]
+type=MinorOpClassSet
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+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
+type=MinorOpClass
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+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
+type=MinorOpClass
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+
+[system.cpu.executeFuncUnits.funcUnits5.timings]
+type=MinorFUTiming
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+mask=0
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+opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
+srcRegsRelativeLats=1
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits6]
+type=MinorFU
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+cantForwardFromFUIndices=
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
+opLat=1
+timings=
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses]
+type=MinorOpClassSet
+children=opClasses0 opClasses1
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
+type=MinorOpClass
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+opClass=IprAccess
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
+type=MinorOpClass
+eventq_index=0
+opClass=InstPrefetch
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=1
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
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+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
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+is_stage2=true
+size=32
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[4]
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
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+is_stage2=false
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
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+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+use_default_range=true
+width=8
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
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+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=2147483648:2415919103
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
+tWTR=7500
+tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 09:18:22
+gem5 started Oct 29 2014 10:29:11
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu.isa: ISA system set to: 0x5c61b00 0x5c61b00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80080000
+info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 51727209160500 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 51.727209 # Number of seconds simulated
+sim_ticks 51727209160500 # Number of ticks simulated
+final_tick 51727209160500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 180889 # Simulator instruction rate (inst/s)
+host_op_rate 212546 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9849373518 # Simulator tick rate (ticks/s)
+host_mem_usage 656984 # Number of bytes of host memory used
+host_seconds 5251.83 # Real time elapsed on the host
+sim_insts 949996153 # Number of instructions simulated
+sim_ops 1116252474 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::realview.ide 424768 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 725248 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 1005696 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 91312008 # Number of bytes read from this memory
+system.physmem.bytes_read::total 93467720 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 9575168 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 9575168 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 57345920 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.inst 101255460 # Number of bytes written to this memory
+system.physmem.bytes_written::total 165427876 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 6637 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 11332 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 15714 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 1426763 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1460446 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 896030 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.inst 1584368 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 2587062 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 8212 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 14021 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 19442 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1765261 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1806935 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 185109 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 185109 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1108622 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 131971 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.inst 1957489 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3198082 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1108622 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 140183 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 14021 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 19442 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 3722750 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 5005018 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1460446 # Number of read requests accepted
+system.physmem.writeReqs 2587062 # Number of write requests accepted
+system.physmem.readBursts 1460446 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 2587062 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 93277376 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 191168 # Total number of bytes read from write queue
+system.physmem.bytesWritten 160708736 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 93467720 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 165427876 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 2987 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 75973 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 39020 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 90929 # Per bank write bursts
+system.physmem.perBankRdBursts::1 88965 # Per bank write bursts
+system.physmem.perBankRdBursts::2 84770 # Per bank write bursts
+system.physmem.perBankRdBursts::3 81753 # Per bank write bursts
+system.physmem.perBankRdBursts::4 95872 # Per bank write bursts
+system.physmem.perBankRdBursts::5 100020 # Per bank write bursts
+system.physmem.perBankRdBursts::6 87194 # Per bank write bursts
+system.physmem.perBankRdBursts::7 85191 # Per bank write bursts
+system.physmem.perBankRdBursts::8 88300 # Per bank write bursts
+system.physmem.perBankRdBursts::9 142631 # Per bank write bursts
+system.physmem.perBankRdBursts::10 90249 # Per bank write bursts
+system.physmem.perBankRdBursts::11 90988 # Per bank write bursts
+system.physmem.perBankRdBursts::12 86795 # Per bank write bursts
+system.physmem.perBankRdBursts::13 81108 # Per bank write bursts
+system.physmem.perBankRdBursts::14 81197 # Per bank write bursts
+system.physmem.perBankRdBursts::15 81497 # Per bank write bursts
+system.physmem.perBankWrBursts::0 153488 # Per bank write bursts
+system.physmem.perBankWrBursts::1 130402 # Per bank write bursts
+system.physmem.perBankWrBursts::2 156905 # Per bank write bursts
+system.physmem.perBankWrBursts::3 130743 # Per bank write bursts
+system.physmem.perBankWrBursts::4 190154 # Per bank write bursts
+system.physmem.perBankWrBursts::5 164896 # Per bank write bursts
+system.physmem.perBankWrBursts::6 144797 # Per bank write bursts
+system.physmem.perBankWrBursts::7 175639 # Per bank write bursts
+system.physmem.perBankWrBursts::8 162274 # Per bank write bursts
+system.physmem.perBankWrBursts::9 194391 # Per bank write bursts
+system.physmem.perBankWrBursts::10 215398 # Per bank write bursts
+system.physmem.perBankWrBursts::11 156932 # Per bank write bursts
+system.physmem.perBankWrBursts::12 147011 # Per bank write bursts
+system.physmem.perBankWrBursts::13 124629 # Per bank write bursts
+system.physmem.perBankWrBursts::14 132966 # Per bank write bursts
+system.physmem.perBankWrBursts::15 130449 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
+system.physmem.totGap 51727207457500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 13 # Read request sizes (log2)
+system.physmem.readPktSize::4 2 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 1460431 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 1 # Write request sizes (log2)
+system.physmem.writePktSize::3 2572 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 2584489 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1416507 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 34555 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 2426 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 627 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 762 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 442 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 403 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 309 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 227 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 153 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 141 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 129 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 128 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 118 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 111 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 97 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 70 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 48 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 72795 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 99197 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 141412 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 149421 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 158127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 155282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 155338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 158469 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 154756 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 163262 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 150399 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 141869 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 140112 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 143384 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 124899 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 123820 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 121368 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 119840 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 5134 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 4523 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 3842 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 3476 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 3047 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 2850 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 2456 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 2169 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 1779 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 1580 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 1367 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 1142 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 843 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 674 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 466 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 357 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 274 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 216 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 179 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 166 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 143 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 125 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 109 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 110 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 83 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 780499 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 325.414218 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 182.439490 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 353.699104 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 309228 39.62% 39.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 174811 22.40% 62.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 65731 8.42% 70.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 36715 4.70% 75.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 26784 3.43% 78.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 18838 2.41% 80.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 14160 1.81% 82.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 15996 2.05% 84.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 118236 15.15% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 780499 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 115810 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 12.584803 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 189.442624 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 115806 100.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::28672-30719 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::49152-51199 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 115810 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 115810 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 21.682704 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 20.755419 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 7.614982 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 58231 50.28% 50.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 24453 21.11% 71.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 18350 15.84% 87.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 9042 7.81% 95.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 1932 1.67% 96.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 855 0.74% 97.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 730 0.63% 98.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 458 0.40% 98.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 355 0.31% 98.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 216 0.19% 98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 209 0.18% 99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 191 0.16% 99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 504 0.44% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 74 0.06% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 53 0.05% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 51 0.04% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 44 0.04% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 3 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 5 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 2 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 14 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 6 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 5 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 8 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 9 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 2 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 115810 # Writes before turning the bus around for reads
+system.physmem.totQLat 16665773749 # Total ticks spent queuing
+system.physmem.totMemAccLat 43993129999 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 7287295000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11434.81 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 30184.81 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.80 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 3.11 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.81 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.20 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.04 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 26.11 # Average write queue length when enqueuing
+system.physmem.readRowHits 1137142 # Number of row buffer hits during reads
+system.physmem.writeRowHits 2050889 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 78.02 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 81.67 # Row buffer hit rate for writes
+system.physmem.avgGap 12780013.64 # Average gap between requests
+system.physmem.pageHitRate 80.33 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 49431156944750 # Time in different power states
+system.physmem.memoryStateTime::REF 1727285040000 # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem.memoryStateTime::ACT 568765880250 # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem.actEnergy::0 2969235360 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 2931337080 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 1620118500 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 1599439875 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 5574566400 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 5793535800 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 8080715520 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 8191044000 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 3378569538240 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 3378569538240 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 1383201002250 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 1386870926445 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 29822988580500 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 29819769348750 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 34603003756770 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 34603725170190 # Total energy per rank (pJ)
+system.physmem.averagePower::0 668.951744 # Core power per rank (mW)
+system.physmem.averagePower::1 668.965690 # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu.inst 740 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 16 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 594629 # Transaction distribution
+system.membus.trans_dist::ReadResp 594629 # Transaction distribution
+system.membus.trans_dist::WriteReq 33870 # Transaction distribution
+system.membus.trans_dist::WriteResp 33870 # Transaction distribution
+system.membus.trans_dist::Writeback 896030 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 1688459 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 1688459 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 39025 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 39026 # Transaction distribution
+system.membus.trans_dist::ReadExReq 901834 # Transaction distribution
+system.membus.trans_dist::ReadExResp 901834 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6924 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7050430 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7180576 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 228843 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 228843 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 7409419 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 251644332 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 251815240 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7251264 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7251264 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 259066504 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 2247 # Total snoops (count)
+system.membus.snoop_fanout::samples 4033943 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 4033943 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 4033943 # Request fanout histogram
+system.membus.reqLayer0.occupancy 113743500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 5505500 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 25619760742 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 15669502469 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer3.occupancy 186602993 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
+system.iobus.trans_dist::ReadReq 40404 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40404 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136687 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136733 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 46 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231004 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231004 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 354274 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334448 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334448 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7492854 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 981194482 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 179049007 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.branchPred.lookups 259878452 # Number of BP lookups
+system.cpu.branchPred.condPredicted 182434681 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 12106293 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 193171007 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 136122005 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 70.467099 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 31463060 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 2055318 # Number of incorrect RAS predictions.
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 183357098 # DTB read hits
+system.cpu.dtb.read_misses 476791 # DTB read misses
+system.cpu.dtb.write_hits 162738381 # DTB write hits
+system.cpu.dtb.write_misses 102414 # DTB write misses
+system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 47228 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 80239 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 828 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 14730 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 23395 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 183833889 # DTB read accesses
+system.cpu.dtb.write_accesses 162840795 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 346095479 # DTB hits
+system.cpu.dtb.misses 579205 # DTB misses
+system.cpu.dtb.accesses 346674684 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 453041166 # ITB inst hits
+system.cpu.itb.inst_misses 137089 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 47228 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 57684 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 391598 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 453178255 # ITB inst accesses
+system.cpu.itb.hits 453041166 # DTB hits
+system.cpu.itb.misses 137089 # DTB misses
+system.cpu.itb.accesses 453178255 # DTB accesses
+system.cpu.numCycles 2529291390 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 949996153 # Number of instructions committed
+system.cpu.committedOps 1116252474 # Number of ops (including micro ops) committed
+system.cpu.discardedOps 97459423 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends 7746 # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles 100926289028 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi 2.662423 # CPI: cycles per instruction
+system.cpu.ipc 0.375598 # IPC: instructions per cycle
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.quiesce 16606 # number of quiesce instructions executed
+system.cpu.tickCycles 1758931949 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 770359441 # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements 24421267 # number of replacements
+system.cpu.icache.tags.tagsinuse 511.933272 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 428216370 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 24421779 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 17.534201 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 20287456250 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 511.933272 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.999870 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.999870 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 477059947 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 477059947 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 428216370 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 428216370 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 428216370 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 428216370 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 428216370 # number of overall hits
+system.cpu.icache.overall_hits::total 428216370 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 24421789 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 24421789 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 24421789 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 24421789 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 24421789 # number of overall misses
+system.cpu.icache.overall_misses::total 24421789 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 323902842267 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 323902842267 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 323902842267 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 323902842267 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 323902842267 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 323902842267 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 452638159 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 452638159 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 452638159 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 452638159 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 452638159 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 452638159 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.053954 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.053954 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.053954 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.053954 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.053954 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.053954 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13262.863022 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13262.863022 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13262.863022 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13262.863022 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13262.863022 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13262.863022 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24421789 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 24421789 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 24421789 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 24421789 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 24421789 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 24421789 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 275014410207 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 275014410207 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 275014410207 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 275014410207 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 275014410207 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 275014410207 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3812415750 # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3812415750 # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3812415750 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total 3812415750 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053954 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053954 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053954 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.053954 # mshr miss rate for demand accesses
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+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 19329.223246 # average overall mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 19329.223246 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 19329.223246 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.tags.replacements 115484 # number of replacements
+system.iocache.tags.tagsinuse 10.452726 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 13140359698000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.516791 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.935936 # Average occupied blocks per requestor
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+system.iocache.tags.occ_percent::total 0.653295 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
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+system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
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+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
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+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
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+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167098.338312 # average ReadReq mshr miss latency
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+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
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+system.iocache.demand_avg_mshr_miss_latency::realview.ide 167098.338312 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 166767.190133 # average overall mshr miss latency
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+system.iocache.overall_avg_mshr_miss_latency::realview.ide 167098.338312 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 166767.190133 # average overall mshr miss latency
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
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+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
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+reset_addr_64=0
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+system_port=system.membus.slave[1]
+
+[system.bridge]
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+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
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+master=system.iobus.slave[0]
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+
+[system.cf0]
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+
+[system.cf0.image]
+type=CowDiskImage
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+image_file=
+read_only=false
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+
+[system.cf0.image.child]
+type=RawDiskImage
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+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
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+domain_id=-1
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+voltage_domain=system.voltage_domain
+
+[system.cpu]
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+trapLatency=13
+wbWidth=8
+workload=
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.branchPred]
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+instShiftAmt=2
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+
+[system.cpu.checker]
+type=O3Checker
+children=dstage2_mmu dtb isa istage2_mmu itb tracer
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+system=system
+tracer=system.cpu.checker.tracer
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+
+[system.cpu.checker.dstage2_mmu]
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+
+[system.cpu.checker.dstage2_mmu.stage2_tlb]
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+
+[system.cpu.checker.dstage2_mmu.stage2_tlb.walker]
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+port=system.cpu.toL2Bus.slave[9]
+
+[system.cpu.checker.dtb]
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+
+[system.cpu.checker.dtb.walker]
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+
+[system.cpu.checker.isa]
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+
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+
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+
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+
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+
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+
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+
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+count=2
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+
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+[system.cpu.fuPool.FUList4.opList25]
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+
+[system.cpu.icache]
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+system=system
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+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
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+
+[system.cpu.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=ArmISA
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+fpsid=1090793632
+id_aa64afr0_el1=0
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+id_isar0=34607377
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+id_isar2=555950401
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+id_pfr0=49
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+midr=1091551472
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+system=system
+
+[system.cpu.istage2_mmu]
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+
+[system.cpu.istage2_mmu.stage2_tlb]
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+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
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+sys=system
+port=system.cpu.toL2Bus.slave[4]
+
+[system.cpu.itb]
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+
+[system.cpu.itb.walker]
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+sys=system
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
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+size=4194304
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.cpu.l2cache.tags]
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+block_size=64
+clk_domain=system.cpu_clk_domain
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+size=4194304
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
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+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
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+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port
+
+[system.cpu.tracer]
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+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
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+header_cycles=1
+use_default_range=true
+width=8
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
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+assoc=8
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+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
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+clk_domain=system.clk_domain
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+size=1024
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
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+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
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+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=2147483648:2415919103
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
+tRRD_L=0
+tRTP=7500
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+tWR=15000
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+tXAW=30000
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+tXS=0
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: 13842443212000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13881966762000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13882255463000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13882829689000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13883384376000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13883639881500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13885195478000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14119823023500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14121701098000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14127958169500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14128186290500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14128405933500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14128812861500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14129226204500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14167422773000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14205629937000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14448292905000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14448293175500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14456513700500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14456513960000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14464465597000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14464465877500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14464466467500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14464466743000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14464466981000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14472409559000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14472410152500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14472410415000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14472410653000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14472410900000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14477663411000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14483940515000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14483940774000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14493678366500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14504940200000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14504941281500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14504941528000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14514859454000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14514859717500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14530591953000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14530592212000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14535730342000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14535730633500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14535731223500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14535731486000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14535731724000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14542816759000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14542817022500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14553011613000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14553012206500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14553012482000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14553012757000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14553013043000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14617580022000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14617580304000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14677231930000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14677232200000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14798881767000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14798974404500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14798974754500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14799704795000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14799705056000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42
+warn: 14799705260500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14799777436500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
+warn: 14799777691500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14799777962500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
+warn: 14799778533000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14799778788500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
+warn: 14799779012000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14799779301000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14799779810000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14799780873500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14799781372500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14799781674500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14848040219000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
+warn: 14848040537000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14848040839000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14848041113000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14848041396500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14848041675500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 09:18:22
+gem5 started Oct 29 2014 10:38:57
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu.checker.isa: ISA system set to: 0x48ecb00 0x48ecb00
+ 0: system.cpu.isa: ISA system set to: 0x48ecb00 0x48ecb00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80080000
+info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 51557114994500 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 51.557115 # Number of seconds simulated
+sim_ticks 51557114994500 # Number of ticks simulated
+final_tick 51557114994500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 81227 # Simulator instruction rate (inst/s)
+host_op_rate 95475 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3758004040 # Simulator tick rate (ticks/s)
+host_mem_usage 668380 # Number of bytes of host memory used
+host_seconds 13719.28 # Real time elapsed on the host
+sim_insts 1114380469 # Number of instructions simulated
+sim_ops 1309844804 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::realview.ide 437568 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 1002304 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 1237760 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 6145632 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 128560840 # Number of bytes read from this memory
+system.physmem.bytes_read::total 137384104 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 6145632 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 6145632 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 102180288 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 102783780 # Number of bytes written to this memory
+system.physmem.bytes_written::total 211790564 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 6837 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 15661 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 19340 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 111978 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2008776 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2162592 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1596567 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data 1608248 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 3311479 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 8487 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 19441 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 24008 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 119200 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2493562 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2664697 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 119200 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 119200 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1981885 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 132406 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1993591 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4107882 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1981885 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 140894 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 19441 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 24008 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 119200 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4487152 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6772580 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 2162592 # Number of read requests accepted
+system.physmem.writeReqs 3311479 # Number of write requests accepted
+system.physmem.readBursts 2162592 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 3311479 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 138204608 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 201280 # Total number of bytes read from write queue
+system.physmem.bytesWritten 207618304 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 137384104 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 211790564 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 3145 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 67428 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 48470 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 140382 # Per bank write bursts
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+system.physmem.perBankRdBursts::3 133921 # Per bank write bursts
+system.physmem.perBankRdBursts::4 130324 # Per bank write bursts
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+system.physmem.perBankRdBursts::6 126217 # Per bank write bursts
+system.physmem.perBankRdBursts::7 133097 # Per bank write bursts
+system.physmem.perBankRdBursts::8 129592 # Per bank write bursts
+system.physmem.perBankRdBursts::9 157619 # Per bank write bursts
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+system.physmem.perBankRdBursts::15 128704 # Per bank write bursts
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+system.physmem.perBankWrBursts::3 188549 # Per bank write bursts
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+system.physmem.perBankWrBursts::5 188791 # Per bank write bursts
+system.physmem.perBankWrBursts::6 176287 # Per bank write bursts
+system.physmem.perBankWrBursts::7 226882 # Per bank write bursts
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+system.physmem.perBankWrBursts::10 253232 # Per bank write bursts
+system.physmem.perBankWrBursts::11 198347 # Per bank write bursts
+system.physmem.perBankWrBursts::12 181957 # Per bank write bursts
+system.physmem.perBankWrBursts::13 175879 # Per bank write bursts
+system.physmem.perBankWrBursts::14 180282 # Per bank write bursts
+system.physmem.perBankWrBursts::15 175595 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 190 # Number of times write queue was full causing retry
+system.physmem.totGap 51557113761500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 13 # Read request sizes (log2)
+system.physmem.readPktSize::4 21272 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 2141307 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 1 # Write request sizes (log2)
+system.physmem.writePktSize::3 2572 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 3308906 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1296550 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 764534 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::3 25837 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 916 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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+system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::52 2852 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 2836 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 2345 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 2139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 1813 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::59 993 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::61 476 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 356 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 474 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 1034839 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 334.179783 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 188.532509 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 356.014667 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 392208 37.90% 37.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 234584 22.67% 60.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 87901 8.49% 69.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 49413 4.77% 73.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 38348 3.71% 77.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 26689 2.58% 80.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 21988 2.12% 82.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 25501 2.46% 84.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 158207 15.29% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1034839 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 135592 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 15.925969 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 128.724301 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 135587 100.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-43007 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 135592 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 135592 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 23.924981 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 20.930688 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 17.164557 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23 101303 74.71% 74.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31 7599 5.60% 80.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39 12845 9.47% 89.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47 3908 2.88% 92.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55 2324 1.71% 94.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63 925 0.68% 95.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71 2932 2.16% 97.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79 1250 0.92% 98.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87 889 0.66% 98.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95 249 0.18% 98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103 327 0.24% 99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111 193 0.14% 99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119 473 0.35% 99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127 16 0.01% 99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135 22 0.02% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143 28 0.02% 99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151 17 0.01% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159 31 0.02% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167 89 0.07% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175 56 0.04% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183 42 0.03% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191 7 0.01% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199 15 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207 2 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215 15 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223 3 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231 6 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239 3 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247 9 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255 5 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263 5 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271 3 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 135592 # Writes before turning the bus around for reads
+system.physmem.totQLat 43990891280 # Total ticks spent queuing
+system.physmem.totMemAccLat 84480522530 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 10797235000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 20371.37 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 39121.37 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.68 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2.66 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 4.11 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.05 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing
+system.physmem.readRowHits 1747291 # Number of row buffer hits during reads
+system.physmem.writeRowHits 2621349 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 80.91 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes
+system.physmem.avgGap 9418422.55 # Average gap between requests
+system.physmem.pageHitRate 80.85 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 49290195125250 # Time in different power states
+system.physmem.memoryStateTime::REF 1721605340000 # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem.memoryStateTime::ACT 545313634750 # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem.actEnergy::0 3951453240 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 3871929600 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 2156050875 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 2112660000 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 8412588600 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 8431020000 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 10640075760 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 10381277520 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 3367460045040 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 3367460045040 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 1383947967870 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 1368871606665 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 29720278968750 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 29733503847000 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 34496847150135 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 34494632385825 # Total energy per rank (pJ)
+system.physmem.averagePower::0 669.099654 # Core power per rank (mW)
+system.physmem.averagePower::1 669.056696 # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 657217 # Transaction distribution
+system.membus.trans_dist::ReadResp 657217 # Transaction distribution
+system.membus.trans_dist::WriteReq 33865 # Transaction distribution
+system.membus.trans_dist::WriteResp 33865 # Transaction distribution
+system.membus.trans_dist::Writeback 1596567 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 1712339 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 1712339 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 48473 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 48476 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1541174 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1541174 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9221519 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9351669 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229018 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 229018 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 9580687 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 341910604 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 342081160 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264064 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7264064 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 349345224 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 2022 # Total snoops (count)
+system.membus.snoop_fanout::samples 5500895 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 5500895 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 5500895 # Request fanout histogram
+system.membus.reqLayer0.occupancy 109641999 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 5450500 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 32462148974 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer2.occupancy 21571101815 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer3.occupancy 186532342 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
+system.iobus.trans_dist::ReadReq 40379 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40379 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136716 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136733 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 17 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 354224 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7492654 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 981079506 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 179002658 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.branchPred.lookups 291488483 # Number of BP lookups
+system.cpu.branchPred.condPredicted 200150149 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 13608043 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 209143322 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 138326751 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 66.139693 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 37688944 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 403819 # Number of incorrect RAS predictions.
+system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
+system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
+system.cpu.checker.dtb.read_hits 206311750 # DTB read hits
+system.cpu.checker.dtb.read_misses 258027 # DTB read misses
+system.cpu.checker.dtb.write_hits 190103200 # DTB write hits
+system.cpu.checker.dtb.write_misses 94684 # DTB write misses
+system.cpu.checker.dtb.flush_tlb 22 # Number of times complete TLB was flushed
+system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.checker.dtb.flush_tlb_mva_asid 127936 # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.dtb.flush_tlb_asid 2418 # Number of times TLB was flushed by ASID
+system.cpu.checker.dtb.flush_entries 89489 # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.checker.dtb.prefetch_faults 10233 # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.checker.dtb.perms_faults 24751 # Number of TLB faults due to permissions restrictions
+system.cpu.checker.dtb.read_accesses 206569777 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 190197884 # DTB write accesses
+system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.checker.dtb.hits 396414950 # DTB hits
+system.cpu.checker.dtb.misses 352711 # DTB misses
+system.cpu.checker.dtb.accesses 396767661 # DTB accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.checker.itb.inst_hits 1114925280 # ITB inst hits
+system.cpu.checker.itb.inst_misses 131008 # ITB inst misses
+system.cpu.checker.itb.read_hits 0 # DTB read hits
+system.cpu.checker.itb.read_misses 0 # DTB read misses
+system.cpu.checker.itb.write_hits 0 # DTB write hits
+system.cpu.checker.itb.write_misses 0 # DTB write misses
+system.cpu.checker.itb.flush_tlb 22 # Number of times complete TLB was flushed
+system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.checker.itb.flush_tlb_mva_asid 127936 # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.itb.flush_tlb_asid 2418 # Number of times TLB was flushed by ASID
+system.cpu.checker.itb.flush_entries 61860 # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.checker.itb.read_accesses 0 # DTB read accesses
+system.cpu.checker.itb.write_accesses 0 # DTB write accesses
+system.cpu.checker.itb.inst_accesses 1115056288 # ITB inst accesses
+system.cpu.checker.itb.hits 1114925280 # DTB hits
+system.cpu.checker.itb.misses 131008 # DTB misses
+system.cpu.checker.itb.accesses 1115056288 # DTB accesses
+system.cpu.checker.numCycles 1310563748 # number of cpu cycles simulated
+system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 220000246 # DTB read hits
+system.cpu.dtb.read_misses 1007031 # DTB read misses
+system.cpu.dtb.write_hits 193886106 # DTB write hits
+system.cpu.dtb.write_misses 416122 # DTB write misses
+system.cpu.dtb.flush_tlb 22 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 127936 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 2418 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 89690 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 112 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 15179 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 87251 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 221007277 # DTB read accesses
+system.cpu.dtb.write_accesses 194302228 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 413886352 # DTB hits
+system.cpu.dtb.misses 1423153 # DTB misses
+system.cpu.dtb.accesses 415309505 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 465588468 # ITB inst hits
+system.cpu.itb.inst_misses 176797 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 22 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 127936 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 2418 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 63536 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 462381 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 465765265 # ITB inst accesses
+system.cpu.itb.hits 465588468 # DTB hits
+system.cpu.itb.misses 176797 # DTB misses
+system.cpu.itb.accesses 465765265 # DTB accesses
+system.cpu.numCycles 2146849645 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.fetch.icacheStallCycles 791511347 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1301628389 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 291488483 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 176015695 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 1268750537 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 29307286 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 4254748 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 27926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 12217982 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 1219824 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 381 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 465107423 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 6746831 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 53918 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 2092636388 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.729302 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.142136 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 1367675983 65.36% 65.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 280886167 13.42% 78.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 86945610 4.15% 82.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 357128628 17.07% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 2092636388 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.135775 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.606297 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 614820490 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 852644163 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 531180111 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 83391963 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 10599661 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 41490545 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 4112846 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 1415541998 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 32718079 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 10599661 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 678805488 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 83662136 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 556428904 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 549849830 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 213290369 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 1391734034 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 7977079 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 7435136 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 893230 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 1023922 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 127479585 # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents 25199 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 1342075875 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2217645602 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1652184740 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1639045 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 1263873564 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 78202308 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 44203192 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 39719264 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 172796539 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 223511224 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 198396121 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 12647992 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 11061331 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1338396177 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 44508712 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1370133902 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 4153047 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 65240654 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 41320787 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 373617 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 2092636388 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.654741 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 0.915536 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 1237717942 59.15% 59.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 455529583 21.77% 80.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 292996726 14.00% 94.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 96986296 4.63% 99.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 9377226 0.45% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 28615 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 2092636388 # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 74528454 34.28% 34.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 90672 0.04% 34.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 26772 0.01% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 287 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 58830485 27.06% 61.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 83911289 38.60% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 945793660 69.03% 69.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2946266 0.22% 69.24% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 129775 0.01% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 114397 0.01% 69.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 224851656 16.41% 85.67% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 196298100 14.33% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total 1370133902 # Type of FU issued
+system.cpu.iq.rate 0.638207 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 217387959 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.158662 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5052021388 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 1447405501 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1347303683 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 2423809 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 923681 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 885699 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1585997449 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 1524411 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 5766333 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads 16996131 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 24128 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 185382 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 8259714 # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads 3623609 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 3385962 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles 10599661 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 11961718 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 7304667 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1383179145 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 223511224 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 198396121 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 39177517 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 185228 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 6936317 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 185382 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4274350 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 5730421 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 10004771 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1356817685 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 220004444 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 11924579 # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp 0 # number of swp insts executed
+system.cpu.iew.exec_nop 274256 # number of nop insts executed
+system.cpu.iew.exec_refs 413901554 # number of memory reference insts executed
+system.cpu.iew.exec_branches 257473473 # Number of branches executed
+system.cpu.iew.exec_stores 193897110 # Number of stores executed
+system.cpu.iew.exec_rate 0.632004 # Inst execution rate
+system.cpu.iew.wb_sent 1349182874 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1348189382 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 579023420 # num instructions producing a value
+system.cpu.iew.wb_consumers 949767765 # num instructions consuming a value
+system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate 0.627985 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.609647 # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitSquashedInsts 62443917 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 44135095 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 9554061 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 2078483160 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.630193 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.269789 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 1396354428 67.18% 67.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 397736022 19.14% 86.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 152396085 7.33% 93.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 44287772 2.13% 95.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 35996912 1.73% 97.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 18656723 0.90% 98.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 10905184 0.52% 98.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 5449343 0.26% 99.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 16700691 0.80% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 2078483160 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 1114380469 # Number of instructions committed
+system.cpu.commit.committedOps 1309844804 # Number of ops (including micro ops) committed
+system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.refs 396651499 # Number of memory references committed
+system.cpu.commit.loads 206515092 # Number of loads committed
+system.cpu.commit.membars 9189565 # Number of memory barriers committed
+system.cpu.commit.branches 249089949 # Number of branches committed
+system.cpu.commit.fp_insts 873640 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 1196978104 # Number of committed integer instructions.
+system.cpu.commit.function_calls 31078874 # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 910428363 69.51% 69.51% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 2554988 0.20% 69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 104143 0.01% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 105769 0.01% 69.72% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.72% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.72% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.72% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 206515092 15.77% 85.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 190136407 14.52% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total 1309844804 # Class of committed instruction
+system.cpu.commit.bw_lim_events 16700691 # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads 3424556806 # The number of ROB reads
+system.cpu.rob.rob_writes 2758622493 # The number of ROB writes
+system.cpu.timesIdled 9031521 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 54213257 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 100967380384 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 1114380469 # Number of Instructions Simulated
+system.cpu.committedOps 1309844804 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 1.926496 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.926496 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.519077 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.519077 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1611998606 # number of integer regfile reads
+system.cpu.int_regfile_writes 948639329 # number of integer regfile writes
+system.cpu.fp_regfile_reads 1420015 # number of floating regfile reads
+system.cpu.fp_regfile_writes 765124 # number of floating regfile writes
+system.cpu.cc_regfile_reads 315259155 # number of cc regfile reads
+system.cpu.cc_regfile_writes 316098925 # number of cc regfile writes
+system.cpu.misc_regfile_reads 6952427793 # number of misc regfile reads
+system.cpu.misc_regfile_writes 45059384 # number of misc regfile writes
+system.cpu.toL2Bus.trans_dist::ReadReq 28539920 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 28531649 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 33865 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 33865 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 9369509 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1712344 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1605675 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 61529 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 61535 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 3074731 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 3074731 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33703094 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 37825776 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 810571 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3115869 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 75455310 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1077469744 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1502191576 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2724416 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10868120 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 2593253856 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 644632 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 42703026 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 9.002705 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.051942 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::9 42587504 99.73% 99.73% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::10 115522 0.27% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 42703026 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 32333793873 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy 871500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 25296093441 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 19876823538 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy 472614279 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
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+system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
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+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500.500000 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 38669.285110 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 38669.285110 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 36295.361841 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 36295.361841 # average overall miss latency
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+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2284719 # number of cycles access was blocked
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+system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.772084 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 1605675 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 9369509 # number of writebacks
+system.cpu.dcache.writebacks::total 9369509 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5628309 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 5628309 # number of ReadReq MSHR hits
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+system.cpu.dcache.WriteReq_mshr_hits::total 15829986 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 265840 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 265840 # number of LoadLockedReq MSHR hits
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+system.cpu.dcache.overall_mshr_hits::total 21458295 # number of overall MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses::total 7083970 # number of ReadReq MSHR misses
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+system.cpu.dcache.WriteReq_mshr_misses::total 3120649 # number of WriteReq MSHR misses
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+system.cpu.dcache.SoftPFReq_mshr_misses::total 2065320 # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 284579 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 284579 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses
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+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3751055249 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3751055249 # number of LoadLockedReq MSHR miss cycles
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+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5729434750 # number of ReadReq MSHR uncacheable cycles
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+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5587276983 # number of WriteReq MSHR uncacheable cycles
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+system.cpu.dcache.overall_mshr_uncacheable_latency::total 11316711733 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035271 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035271 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.017034 # mshr miss rate for WriteReq accesses
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+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813798 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813798 # mshr miss rate for SoftPFReq accesses
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+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052716 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14466.142272 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14466.142272 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47510.555303 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47510.555303 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15305.942177 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15305.942177 # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data inf # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13181.068347 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13181.068347 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17499.500000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17499.500000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24571.371530 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24571.371530 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23011.781335 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23011.781335 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
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+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.tags.replacements 115458 # number of replacements
+system.iocache.tags.tagsinuse 10.450727 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 13090278324000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.528058 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.922669 # Average occupied blocks per requestor
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+system.iocache.tags.occ_percent::realview.ide 0.432667 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.653170 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
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+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 1039786 # Number of tag accesses
+system.iocache.tags.data_accesses 1039786 # Number of data accesses
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+system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits
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+system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency
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+system.iocache.demand_avg_miss_latency::realview.ide 218926.114036 # average overall miss latency
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+system.iocache.overall_avg_miss_latency::realview.ethernet 147150 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 218926.114036 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 218601.812154 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 53350 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 9.717668 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 106664 # number of fast writes performed
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+system.iocache.overall_mshr_miss_latency::realview.ide 1470987863 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 1474793863 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
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+system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
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+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97918.918919 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166911.138432 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 166622.696384 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 95150 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 166911.138432 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 166586.904213 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 95150 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 166911.138432 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 166586.904213 # average overall mshr miss latency
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.quiesce 17164 # number of quiesce instructions executed
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
+atags_addr=134217728
+boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
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+max_loads_all_threads=0
+max_loads_any_thread=0
+needsTSO=false
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
+numRobs=1
+numThreads=1
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=1
+renameToROBDelay=1
+renameWidth=3
+simpoint_start_insts=
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+socket_id=0
+squashWidth=8
+store_set_clear_period=250000
+switched_out=false
+system=system
+tracer=system.cpu1.tracer
+trapLatency=13
+wbWidth=8
+workload=
+dcache_port=system.cpu1.dcache.cpu_side
+icache_port=system.cpu1.icache.cpu_side
+
+[system.cpu1.branchPred]
+type=BranchPredictor
+BTBEntries=2048
+BTBTagSize=18
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+eventq_index=0
+globalCtrBits=2
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=bi-mode
+
+[system.cpu1.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
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+forward_snoops=true
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+mshrs=6
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu1.dcache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=16
+cpu_side=system.cpu1.dcache_port
+mem_side=system.cpu1.toL2Bus.slave[1]
+
+[system.cpu1.dcache.tags]
+type=LRU
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+block_size=64
+clk_domain=system.cpu_clk_domain
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+size=32768
+
+[system.cpu1.dstage2_mmu]
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+stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+tlb=system.cpu1.dtb
+
+[system.cpu1.dstage2_mmu.stage2_tlb]
+type=ArmTLB
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+
+[system.cpu1.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
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+sys=system
+port=system.cpu1.toL2Bus.slave[5]
+
+[system.cpu1.dtb]
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+
+[system.cpu1.dtb.walker]
+type=ArmTableWalker
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+num_squash_per_cycle=2
+sys=system
+port=system.cpu1.toL2Bus.slave[3]
+
+[system.cpu1.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4
+eventq_index=0
+
+[system.cpu1.fuPool.FUList0]
+type=FUDesc
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+opList=system.cpu1.fuPool.FUList0.opList
+
+[system.cpu1.fuPool.FUList0.opList]
+type=OpDesc
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+issueLat=1
+opClass=IntAlu
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+
+[system.cpu1.fuPool.FUList1]
+type=FUDesc
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+opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 system.cpu1.fuPool.FUList1.opList2
+
+[system.cpu1.fuPool.FUList1.opList0]
+type=OpDesc
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+opClass=IntMult
+opLat=3
+
+[system.cpu1.fuPool.FUList1.opList1]
+type=OpDesc
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+issueLat=12
+opClass=IntDiv
+opLat=12
+
+[system.cpu1.fuPool.FUList1.opList2]
+type=OpDesc
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+issueLat=1
+opClass=IprAccess
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+
+[system.cpu1.fuPool.FUList2]
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+opList=system.cpu1.fuPool.FUList2.opList
+
+[system.cpu1.fuPool.FUList2.opList]
+type=OpDesc
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+opClass=MemRead
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+
+[system.cpu1.fuPool.FUList3]
+type=FUDesc
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+eventq_index=0
+opList=system.cpu1.fuPool.FUList3.opList
+
+[system.cpu1.fuPool.FUList3.opList]
+type=OpDesc
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+issueLat=1
+opClass=MemWrite
+opLat=2
+
+[system.cpu1.fuPool.FUList4]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
+eventq_index=0
+opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25
+
+[system.cpu1.fuPool.FUList4.opList00]
+type=OpDesc
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+issueLat=1
+opClass=SimdAdd
+opLat=4
+
+[system.cpu1.fuPool.FUList4.opList01]
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+opClass=SimdAddAcc
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+
+[system.cpu1.fuPool.FUList4.opList02]
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+issueLat=1
+opClass=SimdAlu
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+
+[system.cpu1.fuPool.FUList4.opList03]
+type=OpDesc
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+issueLat=1
+opClass=SimdCmp
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+
+[system.cpu1.fuPool.FUList4.opList04]
+type=OpDesc
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+issueLat=1
+opClass=SimdCvt
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+
+[system.cpu1.fuPool.FUList4.opList05]
+type=OpDesc
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+issueLat=1
+opClass=SimdMisc
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+
+[system.cpu1.fuPool.FUList4.opList06]
+type=OpDesc
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+
+[system.cpu1.fuPool.FUList4.opList07]
+type=OpDesc
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+
+[system.cpu1.fuPool.FUList4.opList08]
+type=OpDesc
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+opClass=SimdShift
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+
+[system.cpu1.fuPool.FUList4.opList09]
+type=OpDesc
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+opClass=SimdShiftAcc
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+
+[system.cpu1.fuPool.FUList4.opList10]
+type=OpDesc
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+
+[system.cpu1.fuPool.FUList4.opList11]
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+opClass=SimdFloatAdd
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+
+[system.cpu1.fuPool.FUList4.opList12]
+type=OpDesc
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+issueLat=1
+opClass=SimdFloatAlu
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+
+[system.cpu1.fuPool.FUList4.opList13]
+type=OpDesc
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+issueLat=1
+opClass=SimdFloatCmp
+opLat=3
+
+[system.cpu1.fuPool.FUList4.opList14]
+type=OpDesc
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+opLat=3
+
+[system.cpu1.fuPool.FUList4.opList15]
+type=OpDesc
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+opClass=SimdFloatDiv
+opLat=3
+
+[system.cpu1.fuPool.FUList4.opList16]
+type=OpDesc
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+issueLat=1
+opClass=SimdFloatMisc
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+
+[system.cpu1.fuPool.FUList4.opList17]
+type=OpDesc
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+issueLat=1
+opClass=SimdFloatMult
+opLat=3
+
+[system.cpu1.fuPool.FUList4.opList18]
+type=OpDesc
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+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu1.fuPool.FUList4.opList19]
+type=OpDesc
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+issueLat=1
+opClass=SimdFloatSqrt
+opLat=9
+
+[system.cpu1.fuPool.FUList4.opList20]
+type=OpDesc
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+issueLat=1
+opClass=FloatAdd
+opLat=5
+
+[system.cpu1.fuPool.FUList4.opList21]
+type=OpDesc
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+issueLat=1
+opClass=FloatCmp
+opLat=5
+
+[system.cpu1.fuPool.FUList4.opList22]
+type=OpDesc
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+issueLat=1
+opClass=FloatCvt
+opLat=5
+
+[system.cpu1.fuPool.FUList4.opList23]
+type=OpDesc
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+issueLat=9
+opClass=FloatDiv
+opLat=9
+
+[system.cpu1.fuPool.FUList4.opList24]
+type=OpDesc
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+issueLat=33
+opClass=FloatSqrt
+opLat=33
+
+[system.cpu1.fuPool.FUList4.opList25]
+type=OpDesc
+eventq_index=0
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu1.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=1
+is_top_level=true
+max_miss_count=0
+mshrs=2
+prefetch_on_access=false
+prefetcher=Null
+response_latency=1
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu1.icache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.icache_port
+mem_side=system.cpu1.toL2Bus.slave[0]
+
+[system.cpu1.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=1
+sequential_access=false
+size=32768
+
+[system.cpu1.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu1.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu1.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+tlb=system.cpu1.itb
+
+[system.cpu1.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
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+size=32
+walker=system.cpu1.istage2_mmu.stage2_tlb.walker
+
+[system.cpu1.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu1.toL2Bus.slave[4]
+
+[system.cpu1.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu1.toL2Bus.slave[2]
+
+[system.cpu1.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu1.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu1.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu1.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu1.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu1.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu1.l2cache.cpu_side
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+
+[system.cpu1.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+use_default_range=true
+width=8
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
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+forward_snoops=false
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+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
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+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.l2c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
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+prefetch_on_access=false
+prefetcher=Null
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+sequential_access=false
+size=4194304
+system=system
+tags=system.l2c.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=2147483648:2415919103
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
+tWTR=7500
+tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.l2c.cpu_side
+slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: allocating bonus target for snoop
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 09:18:22
+gem5 started Oct 29 2014 11:56:54
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu0.isa: ISA system set to: 0x5878b00 0x5878b00
+ 0: system.cpu1.isa: ISA system set to: 0x5878b00 0x5878b00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80080000
+info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 47379674621500 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 47.379675 # Number of seconds simulated
+sim_ticks 47379674621500 # Number of ticks simulated
+final_tick 47379674621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 109387 # Simulator instruction rate (inst/s)
+host_op_rate 128661 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5550125892 # Simulator tick rate (ticks/s)
+host_mem_usage 850512 # Number of bytes of host memory used
+host_seconds 8536.68 # Real time elapsed on the host
+sim_insts 933798389 # Number of instructions simulated
+sim_ops 1098335322 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 528 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_read::cpu0.inst 24331 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 387383 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::cpu1.dtb.walker 7139 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 9768 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 11230 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 273690 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 615501 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2165845 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 24331 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 11230 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 35561 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1192259 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 144167 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 1406163 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 723417 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3466006 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1192259 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 154132 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 7452 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 11052 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 24331 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1793546 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 808334 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 7139 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 9768 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 11230 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 997107 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 615501 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 5631851 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1619423 # Number of read requests accepted
+system.physmem.writeReqs 2568188 # Number of write requests accepted
+system.physmem.readBursts 1619423 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 2568188 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 103371328 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 271744 # Total number of bytes read from write queue
+system.physmem.bytesWritten 158872640 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 102617016 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 164218256 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 4246 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 85771 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 103144 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 111705 # Per bank write bursts
+system.physmem.perBankRdBursts::1 107185 # Per bank write bursts
+system.physmem.perBankRdBursts::2 95216 # Per bank write bursts
+system.physmem.perBankRdBursts::3 93593 # Per bank write bursts
+system.physmem.perBankRdBursts::4 97040 # Per bank write bursts
+system.physmem.perBankRdBursts::5 109538 # Per bank write bursts
+system.physmem.perBankRdBursts::6 103640 # Per bank write bursts
+system.physmem.perBankRdBursts::7 104459 # Per bank write bursts
+system.physmem.perBankRdBursts::8 87345 # Per bank write bursts
+system.physmem.perBankRdBursts::9 119689 # Per bank write bursts
+system.physmem.perBankRdBursts::10 87550 # Per bank write bursts
+system.physmem.perBankRdBursts::11 102455 # Per bank write bursts
+system.physmem.perBankRdBursts::12 98167 # Per bank write bursts
+system.physmem.perBankRdBursts::13 96293 # Per bank write bursts
+system.physmem.perBankRdBursts::14 97699 # Per bank write bursts
+system.physmem.perBankRdBursts::15 103603 # Per bank write bursts
+system.physmem.perBankWrBursts::0 151797 # Per bank write bursts
+system.physmem.perBankWrBursts::1 157102 # Per bank write bursts
+system.physmem.perBankWrBursts::2 173467 # Per bank write bursts
+system.physmem.perBankWrBursts::3 129226 # Per bank write bursts
+system.physmem.perBankWrBursts::4 217724 # Per bank write bursts
+system.physmem.perBankWrBursts::5 151423 # Per bank write bursts
+system.physmem.perBankWrBursts::6 153455 # Per bank write bursts
+system.physmem.perBankWrBursts::7 181552 # Per bank write bursts
+system.physmem.perBankWrBursts::8 127836 # Per bank write bursts
+system.physmem.perBankWrBursts::9 166575 # Per bank write bursts
+system.physmem.perBankWrBursts::10 140595 # Per bank write bursts
+system.physmem.perBankWrBursts::11 139064 # Per bank write bursts
+system.physmem.perBankWrBursts::12 135611 # Per bank write bursts
+system.physmem.perBankWrBursts::13 129688 # Per bank write bursts
+system.physmem.perBankWrBursts::14 173219 # Per bank write bursts
+system.physmem.perBankWrBursts::15 154051 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 280 # Number of times write queue was full causing retry
+system.physmem.totGap 47379673169000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 37 # Read request sizes (log2)
+system.physmem.readPktSize::4 21333 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 1598053 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 2 # Write request sizes (log2)
+system.physmem.writePktSize::3 2601 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 2565585 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 575288 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::2 198870 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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+system.physmem.wrQLenPdf::57 1704 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 1382 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 1113 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::61 602 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 472 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 674 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 968355 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 270.813741 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 146.322670 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 334.242545 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 500729 51.71% 51.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 182951 18.89% 70.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 62910 6.50% 77.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 30320 3.13% 80.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 27676 2.86% 83.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 15651 1.62% 84.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 12433 1.28% 85.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 15606 1.61% 87.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 120079 12.40% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 968355 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 90300 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 17.886467 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 201.343157 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 90297 100.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-16383 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 90300 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 90300 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 27.490421 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 23.640759 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 19.748039 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23 56859 62.97% 62.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31 8057 8.92% 71.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39 12273 13.59% 85.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47 3990 4.42% 89.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55 1898 2.10% 92.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63 944 1.05% 93.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71 2681 2.97% 96.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79 1258 1.39% 97.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87 729 0.81% 98.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95 233 0.26% 98.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103 328 0.36% 98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111 174 0.19% 99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119 473 0.52% 99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127 16 0.02% 99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135 44 0.05% 99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143 33 0.04% 99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151 16 0.02% 99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159 34 0.04% 99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167 77 0.09% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175 57 0.06% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183 40 0.04% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191 6 0.01% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199 21 0.02% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215 22 0.02% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223 2 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231 4 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239 3 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247 7 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255 9 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263 3 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271 6 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-279 3 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 90300 # Writes before turning the bus around for reads
+system.physmem.totQLat 65880977516 # Total ticks spent queuing
+system.physmem.totMemAccLat 96165546266 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 8075885000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 40788.70 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 59538.70 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.18 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2.17 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.47 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.04 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 3.63 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.06 # Average write queue length when enqueuing
+system.physmem.readRowHits 1266207 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1862998 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 78.39 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.05 # Row buffer hit rate for writes
+system.physmem.avgGap 11314248.90 # Average gap between requests
+system.physmem.pageHitRate 76.37 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 45458713155000 # Time in different power states
+system.physmem.memoryStateTime::REF 1582111440000 # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem.memoryStateTime::ACT 338849669500 # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem.actEnergy::0 3771472320 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 3549283920 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 2057847000 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 1936613250 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 6414501600 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 6183847800 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 8526034080 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 7559820720 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 3094609976640 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 3094609976640 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 1215510046335 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 1201972779180 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 27361567580250 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 27373442376000 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 31692457458225 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 31689254697510 # Total energy per rank (pJ)
+system.physmem.averagePower::0 668.904083 # Core power per rank (mW)
+system.physmem.averagePower::1 668.836485 # Core power per rank (mW)
+system.membus.trans_dist::ReadReq 1503713 # Transaction distribution
+system.membus.trans_dist::ReadResp 1503713 # Transaction distribution
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+system.membus.trans_dist::WriteResp 38586 # Transaction distribution
+system.membus.trans_dist::Writeback 882638 # Transaction distribution
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+system.membus.trans_dist::WriteInvalidateResp 1682947 # Transaction distribution
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+system.membus.trans_dist::SCUpgradeReq 331267 # Transaction distribution
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+system.membus.trans_dist::ReadExResp 155861 # Transaction distribution
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+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 8087433 # Packet count per connected master and slave (bytes)
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+system.membus.pkt_count::total 8466359 # Packet count per connected master and slave (bytes)
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+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 259532552 # Cumulative packet size per connected master and slave (bytes)
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+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7302720 # Cumulative packet size per connected master and slave (bytes)
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+system.membus.pkt_size::total 267044039 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 618323 # Total snoops (count)
+system.membus.snoop_fanout::samples 4885385 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 4885385 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 4885385 # Request fanout histogram
+system.membus.reqLayer0.occupancy 98770920 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 45500 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 21644945 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 25191464236 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer2.occupancy 16556458898 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer3.occupancy 187451430 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
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+system.l2c.tags.sampled_refs 1449367 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 5.258155 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 406522254 # number of UpgradeReq MSHR miss cycles
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+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 99686358 # number of SCUpgradeReq MSHR miss cycles
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1103207000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4952355997 # number of ReadReq MSHR uncacheable cycles
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 415818753 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 6475689500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4782466503 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 497465997 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 5279932500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1103207000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9734822500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4307750 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 913284750 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 11755622000 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.422112 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.655451 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.069216 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.220588 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.246804 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.391250 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.583710 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.048455 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.164922 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.200507 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.210253 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.575641 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.554899 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.565023 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.571360 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.563483 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.567819 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.631869 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.558384 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.598329 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.422112 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.655451 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.069216 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.278016 # mshr miss rate for demand accesses
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+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.391250 # mshr miss rate for demand accesses
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+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.048455 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.215360 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.200507 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.224847 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.422112 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.655451 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.069216 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.278016 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.246804 # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::cpu1.data 0.215360 # mshr miss rate for overall accesses
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80451.468412 # average ReadReq mshr miss latency
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 82361.036390 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 81359.470904 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 101975.362824 # average ReadReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10304.809373 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10376.553947 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10340.877759 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10367.861265 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10379.670762 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10373.130168 # average SCUpgradeReq mshr miss latency
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+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67723.577249 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 68292.905223 # average ReadExReq mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 84156.419378 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76726.958771 # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496 # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 82361.036390 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 76827.288132 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 98604.649565 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 84156.419378 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76726.958771 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 82361.036390 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76827.288132 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 98604.649565 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq 7757807 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 7750243 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38586 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38586 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 2284318 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 1682954 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 1576219 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 430271 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 347651 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 777922 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 191 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 316482 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 316482 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 11788342 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9897130 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 21685472 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 381410986 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 320139805 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 701550791 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 1633796 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 12761522 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.009063 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.094770 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 12645858 99.09% 99.09% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 115664 0.91% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 12761522 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 21862906503 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 6130500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 19509958221 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 17925237290 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 40417 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40417 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136643 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136782 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 139 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48150 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 123084 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 354398 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48170 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 156191 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7497229 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36599000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 982013630 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 93033000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 179230570 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.cpu0.branchPred.lookups 146587108 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 96932064 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 7164901 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 103453764 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 67642054 # Number of BTB hits
+system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu0.branchPred.BTBHitPct 65.383850 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 20270932 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 203679 # Number of incorrect RAS predictions.
+system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 106134781 # DTB read hits
+system.cpu0.dtb.read_misses 438400 # DTB read misses
+system.cpu0.dtb.write_hits 87107060 # DTB write hits
+system.cpu0.dtb.write_misses 166320 # DTB write misses
+system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 41289 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 449 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 7213 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 39737 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 106573181 # DTB read accesses
+system.cpu0.dtb.write_accesses 87273380 # DTB write accesses
+system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dtb.hits 193241841 # DTB hits
+system.cpu0.dtb.misses 604720 # DTB misses
+system.cpu0.dtb.accesses 193846561 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.inst_hits 230537480 # ITB inst hits
+system.cpu0.itb.inst_misses 86000 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 29668 # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults 226388 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.inst_accesses 230623480 # ITB inst accesses
+system.cpu0.itb.hits 230537480 # DTB hits
+system.cpu0.itb.misses 86000 # DTB misses
+system.cpu0.itb.accesses 230623480 # DTB accesses
+system.cpu0.numCycles 786965482 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.fetch.icacheStallCycles 90387711 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 647691070 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 146587108 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 87912986 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 665690431 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 15471710 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 1846295 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 143165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 6476529 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 786234 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 320116 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 230311190 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 1742140 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 28723 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 773386336 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.980975 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 1.219702 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 409957196 53.01% 53.01% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 140998975 18.23% 71.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 49617031 6.42% 77.66% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 172813134 22.34% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::total 773386336 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.186269 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.823023 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 108593313 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 378356513 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 240969730 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 39977542 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 5489238 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 21224089 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 2292433 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 668689408 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 25030555 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 5489238 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 146312922 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 57383456 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 250430469 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 242520551 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 71249700 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 650266707 # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts 6336504 # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents 9477139 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 381865 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 840506 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 33815177 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents 14484 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 619540415 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 1001273329 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 768127423 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 806411 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 558016180 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 61524234 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 16309942 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 14158531 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 81487680 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 106551444 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 90697387 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 9851628 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 8566406 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 626998472 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 16435650 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 631073777 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 2910747 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 54340762 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 37568320 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 303534 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 773386336 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.815988 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.066561 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 429333552 55.51% 55.51% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 143479671 18.55% 74.07% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 122471651 15.84% 89.90% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 69760577 9.02% 98.92% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 8335355 1.08% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 5527 0.00% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 3 0.00% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 773386336 # Number of insts issued each cycle
+system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 65856729 45.73% 45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 73447 0.05% 45.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 22232 0.02% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 47 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 37876967 26.30% 72.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 40192311 27.91% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 431505224 68.38% 68.38% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 1606072 0.25% 68.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 80666 0.01% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 12 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 1 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 46680 0.01% 68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 109370672 17.33% 85.98% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 88464450 14.02% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::total 631073777 # Type of FU issued
+system.cpu0.iq.rate 0.801908 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 144021733 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.228217 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 2181305203 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 697468177 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 613392938 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 1161167 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 463347 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 426941 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 774373560 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 721950 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 2923759 # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu0.iew.lsq.thread0.squashedLoads 13150556 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 17424 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 157648 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 6172607 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu0.iew.lsq.thread0.rescheduledLoads 2931375 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 4759724 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu0.iew.iewSquashCycles 5489238 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 8266633 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 4717216 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 643560247 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 106551444 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 90697387 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 13867290 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 61805 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 4582618 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 157648 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 2155844 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 3101202 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 5257046 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 622852330 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 106129153 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 7624905 # Number of squashed instructions skipped in execute
+system.cpu0.iew.exec_swp 0 # number of swp insts executed
+system.cpu0.iew.exec_nop 126125 # number of nop insts executed
+system.cpu0.iew.exec_refs 193235409 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 117777762 # Number of branches executed
+system.cpu0.iew.exec_stores 87106256 # Number of stores executed
+system.cpu0.iew.exec_rate 0.791461 # Inst execution rate
+system.cpu0.iew.wb_sent 614619625 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 613819879 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 298670143 # num instructions producing a value
+system.cpu0.iew.wb_consumers 489758313 # num instructions consuming a value
+system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu0.iew.wb_rate 0.779983 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.609832 # average fanout of values written-back
+system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu0.commit.commitSquashedInsts 50622338 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 16132116 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 4918284 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 763797135 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.766621 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.569865 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 508551807 66.58% 66.58% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 131505056 17.22% 83.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 56862924 7.44% 91.24% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 18814885 2.46% 93.71% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 13980697 1.83% 95.54% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 9342143 1.22% 96.76% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 6309382 0.83% 97.59% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 4063980 0.53% 98.12% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 14366261 1.88% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::total 763797135 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 498729441 # Number of instructions committed
+system.cpu0.commit.committedOps 585543302 # Number of ops (including micro ops) committed
+system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu0.commit.refs 177925668 # Number of memory references committed
+system.cpu0.commit.loads 93400888 # Number of loads committed
+system.cpu0.commit.membars 4075726 # Number of memory barriers committed
+system.cpu0.commit.branches 111746625 # Number of branches committed
+system.cpu0.commit.fp_insts 417930 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 537600399 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 15117239 # Number of function calls committed.
+system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 406177320 69.37% 69.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 1336444 0.23% 69.60% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv 63141 0.01% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc 40729 0.01% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 93400888 15.95% 85.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 84524780 14.44% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::total 585543302 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 14366261 # number cycles where commit BW limit reached
+system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu0.rob.rob_reads 1380974813 # The number of ROB reads
+system.cpu0.rob.rob_writes 1281884282 # The number of ROB writes
+system.cpu0.timesIdled 846185 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 13579146 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 93972383800 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 498729441 # Number of Instructions Simulated
+system.cpu0.committedOps 585543302 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 1.577941 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 1.577941 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.633737 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.633737 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 735405419 # number of integer regfile reads
+system.cpu0.int_regfile_writes 437369435 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 697220 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 340900 # number of floating regfile writes
+system.cpu0.cc_regfile_reads 134840784 # number of cc regfile reads
+system.cpu0.cc_regfile_writes 135500502 # number of cc regfile writes
+system.cpu0.misc_regfile_reads 3071585466 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 16203449 # number of misc regfile writes
+system.cpu0.toL2Bus.trans_dist::ReadReq 15637085 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 12009481 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 33046 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 33046 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 3548344 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 4365503 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1683195 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 1040668 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 461767 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 386684 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 535373 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1436156 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1297014 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 13051451 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18246800 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 419537 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1341455 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 33059243 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 416613216 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 664873226 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1541384 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4934904 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 1087962730 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 9586812 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 27467610 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 5.337349 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.472805 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5 18201451 66.27% 66.27% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6 9266159 33.73% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
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+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 61642.520514 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23582.064847 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32082.226080 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 35601.440437 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34126.366499 # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.dcache.tags.replacements 6421778 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 503.783649 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 165065902 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 6422290 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 25.702032 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 1750084500 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.783649 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983952 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.983952 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses 369226254 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 369226254 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 86280065 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 86280065 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 73574281 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 73574281 # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 230862 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 230862 # number of SoftPFReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 1040668 # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::total 1040668 # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1948592 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 1948592 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1987329 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 1987329 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 159854346 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 159854346 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 160085208 # number of overall hits
+system.cpu0.dcache.overall_hits::total 160085208 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 7331765 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 7331765 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 7708797 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 7708797 # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 740087 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total 740087 # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 294779 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 294779 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 214098 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 214098 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 15040562 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 15040562 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 15780649 # number of overall misses
+system.cpu0.dcache.overall_misses::total 15780649 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 115068880578 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 115068880578 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 135208359707 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 135208359707 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4223400082 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 4223400082 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4534810216 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 4534810216 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4219500 # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4219500 # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 250277240285 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 250277240285 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 250277240285 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 250277240285 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 93611830 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 93611830 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 81283078 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 81283078 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 970949 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total 970949 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1040668 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::total 1040668 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2243371 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 2243371 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2201427 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 2201427 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 174894908 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 174894908 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 175865857 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 175865857 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.078321 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.078321 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.094839 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.094839 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.762231 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.762231 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.131400 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.131400 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097254 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097254 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085998 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.085998 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.089731 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.089731 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15694.567485 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15694.567485 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17539.488938 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 17539.488938 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14327.343814 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14327.343814 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21181.002233 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21181.002233 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16640.152162 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 16640.152162 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15859.755849 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 15859.755849 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 17082084 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 19003690 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 950552 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 748671 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.970699 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 25.383232 # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes 1040668 # number of fast writes performed
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks 3548346 # number of writebacks
+system.cpu0.dcache.writebacks::total 3548346 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3808172 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 3808172 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6155071 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 6155071 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 150940 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 150940 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 9963243 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 9963243 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 9963243 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 9963243 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3523593 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 3523593 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1532184 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 1532184 # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 733570 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 733570 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 143839 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 143839 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 214091 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 214091 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 5055777 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 5055777 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 5789347 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 5789347 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48006705459 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 48006705459 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27570008615 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27570008615 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18661725527 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18661725527 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 57519686561 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 57519686561 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1764532424 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1764532424 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4095364784 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4095364784 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4027500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4027500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 75576714074 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 75576714074 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94238439601 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 94238439601 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5807383412 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5807383412 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5600359921 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5600359921 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11407743333 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11407743333 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037640 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037640 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018850 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018850 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.755519 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.755519 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064117 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064117 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097251 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097251 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028908 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.028908 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032919 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.032919 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13624.361684 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13624.361684 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17993.928024 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17993.928024 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25439.597485 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25439.597485 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12267.413038 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12267.413038 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19129.084287 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19129.084287 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14948.585366 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14948.585366 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16277.904849 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16277.904849 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.branchPred.lookups 126883394 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 85166335 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 6223569 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 90014178 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 58475937 # Number of BTB hits
+system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu1.branchPred.BTBHitPct 64.963029 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 16774062 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 171946 # Number of incorrect RAS predictions.
+system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.inst_hits 0 # ITB inst hits
+system.cpu1.dtb.inst_misses 0 # ITB inst misses
+system.cpu1.dtb.read_hits 93423769 # DTB read hits
+system.cpu1.dtb.read_misses 385141 # DTB read misses
+system.cpu1.dtb.write_hits 77506370 # DTB write hits
+system.cpu1.dtb.write_misses 166753 # DTB write misses
+system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 38053 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 411 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 6413 # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults 42956 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 93808910 # DTB read accesses
+system.cpu1.dtb.write_accesses 77673123 # DTB write accesses
+system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dtb.hits 170930139 # DTB hits
+system.cpu1.dtb.misses 551894 # DTB misses
+system.cpu1.dtb.accesses 171482033 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.inst_hits 200532583 # ITB inst hits
+system.cpu1.itb.inst_misses 85074 # ITB inst misses
+system.cpu1.itb.read_hits 0 # DTB read hits
+system.cpu1.itb.read_misses 0 # DTB read misses
+system.cpu1.itb.write_hits 0 # DTB write hits
+system.cpu1.itb.write_misses 0 # DTB write misses
+system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 26827 # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults 221691 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses 0 # DTB read accesses
+system.cpu1.itb.write_accesses 0 # DTB write accesses
+system.cpu1.itb.inst_accesses 200617657 # ITB inst accesses
+system.cpu1.itb.hits 200532583 # DTB hits
+system.cpu1.itb.misses 85074 # DTB misses
+system.cpu1.itb.accesses 200617657 # DTB accesses
+system.cpu1.numCycles 671498045 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.fetch.icacheStallCycles 76057268 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 563958948 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 126883394 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 75249999 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 570112426 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 13401984 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 1796129 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 140886 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 6366912 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 711415 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 284551 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 200289545 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 1511940 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 28568 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 662170579 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.001134 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 1.225253 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 344731960 52.06% 52.06% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 123888404 18.71% 70.77% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 41617512 6.29% 77.06% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 151932703 22.94% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::total 662170579 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.188956 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.839852 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 93652150 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 319101856 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 208055943 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 36600277 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 4760353 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 17735520 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 1981049 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 585316730 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 21686226 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 4760353 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 127273008 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 44978505 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 215016897 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 210494675 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 59647141 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 569572737 # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts 5483527 # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents 8310630 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 236317 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 296206 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 25698514 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents 13591 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 543172602 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 884661173 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 673765883 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 933137 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 489609146 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 53563450 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 15680851 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 13859127 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 73666324 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 93680638 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 80687792 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 8658535 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 7660349 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 547737456 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 15869030 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 553093233 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 2542275 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 47705580 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 32628806 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 263861 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 662170579 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.835273 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.067651 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 358036858 54.07% 54.07% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 130663379 19.73% 73.80% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 105371554 15.91% 89.72% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 60712008 9.17% 98.88% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 7383178 1.11% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 3602 0.00% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 662170579 # Number of insts issued each cycle
+system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 55137578 43.73% 43.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 43337 0.03% 43.76% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 11462 0.01% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 21 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 33948572 26.92% 70.70% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 36949037 29.30% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu1.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 376818141 68.13% 68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 1181294 0.21% 68.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 70304 0.01% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 78003 0.01% 68.37% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.37% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.37% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.37% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 96248927 17.40% 85.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 78696516 14.23% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::total 553093233 # Type of FU issued
+system.cpu1.iq.rate 0.823671 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 126090007 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.227972 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 1895671563 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 610922154 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 537423673 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 1317762 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 530370 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 489519 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 678367586 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 815653 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 2464833 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu1.iew.lsq.thread0.squashedLoads 11666973 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 15967 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 141534 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 5620813 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu1.iew.lsq.thread0.rescheduledLoads 2485085 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 4066782 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu1.iew.iewSquashCycles 4760353 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 6088373 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 2643428 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 563729528 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 93680638 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 80687792 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 13644540 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 61293 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 2520664 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 141534 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 1916152 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 2651693 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 4567845 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 545961284 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 93419699 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 6590982 # Number of squashed instructions skipped in execute
+system.cpu1.iew.exec_swp 0 # number of swp insts executed
+system.cpu1.iew.exec_nop 123042 # number of nop insts executed
+system.cpu1.iew.exec_refs 170926883 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 102016204 # Number of branches executed
+system.cpu1.iew.exec_stores 77507184 # Number of stores executed
+system.cpu1.iew.exec_rate 0.813050 # Inst execution rate
+system.cpu1.iew.wb_sent 538581721 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 537913192 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 259879872 # num instructions producing a value
+system.cpu1.iew.wb_consumers 425846883 # num instructions consuming a value
+system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu1.iew.wb_rate 0.801064 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.610266 # average fanout of values written-back
+system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu1.commit.commitSquashedInsts 44555907 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 15605169 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 4282930 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 653744993 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.784392 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.576833 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 427404365 65.38% 65.38% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 119117281 18.22% 83.60% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 49133324 7.52% 91.11% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 16524443 2.53% 93.64% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 11998035 1.84% 95.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 8093886 1.24% 96.72% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 5471403 0.84% 97.55% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 3473274 0.53% 98.08% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 12528982 1.92% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::total 653744993 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 435068948 # Number of instructions committed
+system.cpu1.commit.committedOps 512792020 # Number of ops (including micro ops) committed
+system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu1.commit.refs 157080643 # Number of memory references committed
+system.cpu1.commit.loads 82013664 # Number of loads committed
+system.cpu1.commit.membars 3580423 # Number of memory barriers committed
+system.cpu1.commit.branches 96770677 # Number of branches committed
+system.cpu1.commit.fp_insts 477739 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 470356347 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 12430117 # Number of function calls committed.
+system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 354618766 69.15% 69.15% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 966577 0.19% 69.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 56200 0.01% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 69792 0.01% 69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 82013664 15.99% 85.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 75066979 14.64% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::total 512792020 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 12528982 # number cycles where commit BW limit reached
+system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu1.rob.rob_reads 1194813735 # The number of ROB reads
+system.cpu1.rob.rob_writes 1123082959 # The number of ROB writes
+system.cpu1.timesIdled 724798 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 9327466 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 94087851225 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 435068948 # Number of Instructions Simulated
+system.cpu1.committedOps 512792020 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 1.543429 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 1.543429 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.647908 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.647908 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 645605353 # number of integer regfile reads
+system.cpu1.int_regfile_writes 381721004 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 775313 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 445860 # number of floating regfile writes
+system.cpu1.cc_regfile_reads 118711593 # number of cc regfile reads
+system.cpu1.cc_regfile_writes 119446570 # number of cc regfile writes
+system.cpu1.misc_regfile_reads 2680324006 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 15740060 # number of misc regfile writes
+system.cpu1.toL2Bus.trans_dist::ReadReq 14195138 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 10319504 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 5540 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 5540 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 3043633 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 4072942 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp 7 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1683351 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 535551 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 440112 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 381311 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 495883 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1326326 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1162072 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11031290 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15072798 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 408972 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1223990 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 27737050 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 352998000 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 552975725 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1478304 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4387432 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 911839461 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 10107713 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 25138246 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 5.388398 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.487386 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5 15374612 61.16% 61.16% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6 9763634 38.84% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 25138246 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 11278575992 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 196968741 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer0.occupancy 8281966249 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer1.occupancy 7967439656 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer2.occupancy 225433169 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer3.occupancy 677266087 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu1.icache.tags.replacements 5515063 # number of replacements
+system.cpu1.icache.tags.tagsinuse 501.927395 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 194540892 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 5515575 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 35.271190 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 8512592975000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.927395 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980327 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.980327 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 87 # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses 406089111 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 406089111 # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst 194540892 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 194540892 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 194540892 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 194540892 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 194540892 # number of overall hits
+system.cpu1.icache.overall_hits::total 194540892 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 5745874 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 5745874 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 5745874 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 5745874 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 5745874 # number of overall misses
+system.cpu1.icache.overall_misses::total 5745874 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 49972720911 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 49972720911 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 49972720911 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 49972720911 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 49972720911 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 49972720911 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 200286766 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 200286766 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 200286766 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 200286766 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 200286766 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 200286766 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028688 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.028688 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028688 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.028688 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028688 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.028688 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8697.148756 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 8697.148756 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8697.148756 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 8697.148756 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8697.148756 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 8697.148756 # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 4058036 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 525950 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.715631 # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes 0 # number of fast writes performed
+system.cpu1.icache.cache_copies 0 # number of cache copies performed
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 230295 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total 230295 # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst 230295 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total 230295 # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst 230295 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total 230295 # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5515579 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 5515579 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 5515579 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 5515579 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 5515579 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total 5515579 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 40507461081 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 40507461081 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 40507461081 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 40507461081 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 40507461081 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 40507461081 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6176248 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6176248 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6176248 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total 6176248 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027538 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027538 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027538 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.027538 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027538 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.027538 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7344.190171 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7344.190171 # average ReadReq mshr miss latency
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+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 88845492183 # number of HardPFReq MSHR miss cycles
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+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2271880441 # number of UpgradeReq MSHR miss cycles
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+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 527891053 # number of ReadReq MSHR uncacheable cycles
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+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 592984543 # number of WriteReq MSHR uncacheable cycles
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+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028800 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.068143 # mshr miss rate for ReadReq accesses
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+system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
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+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.587027 # mshr miss rate for UpgradeReq accesses
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+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.030928 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.265165 # mshr miss rate for demand accesses
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+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.068143 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.030928 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.265165 # mshr miss rate for overall accesses
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+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21735.445418 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26775.298889 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26588.275709 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32053.702935 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 32053.702935 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17563.550939 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17563.550939 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13637.442900 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13637.442900 # average SCUpgradeReq mshr miss latency
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+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183352.941176 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36902.824973 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36902.824973 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313 # average overall mshr miss latency
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+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21735.445418 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28528.009575 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28138.464180 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 58266.582195 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21735.445418 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28528.009575 # average overall mshr miss latency
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+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
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+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
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+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dcache.tags.replacements 5270583 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 418.735038 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 145844611 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 5271093 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 27.668761 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 8472891797000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 418.735038 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.817842 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.817842 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 326008687 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 326008687 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 76031229 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 76031229 # number of ReadReq hits
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+system.cpu1.dcache.WriteReq_hits::total 65289331 # number of WriteReq hits
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+system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 535551 # number of WriteInvalidateReq hits
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+system.cpu1.dcache.StoreCondReq_hits::total 1734724 # number of StoreCondReq hits
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+system.cpu1.dcache.ReadReq_misses::total 6360074 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 7315323 # number of WriteReq misses
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+system.cpu1.dcache.SoftPFReq_misses::total 690767 # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 239985 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 239985 # number of LoadLockedReq misses
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+system.cpu1.dcache.demand_misses::cpu1.data 13675397 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 13675397 # number of demand (read+write) misses
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+system.cpu1.dcache.overall_misses::total 14366164 # number of overall misses
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+system.cpu1.dcache.ReadReq_miss_latency::total 96502365280 # number of ReadReq miss cycles
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+system.cpu1.dcache.WriteReq_miss_latency::total 122289774326 # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3384586861 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 3384586861 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4391846948 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 4391846948 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4067000 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4067000 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 218792139606 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 218792139606 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 218792139606 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 218792139606 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 82391303 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 82391303 # number of ReadReq accesses(hits+misses)
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+system.cpu1.dcache.WriteReq_accesses::total 72604654 # number of WriteReq accesses(hits+misses)
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+system.cpu1.dcache.SoftPFReq_accesses::total 862592 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 535551 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::total 535551 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1984863 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 1984863 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1941024 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 1941024 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 154995957 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 154995957 # number of demand (read+write) accesses
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+system.cpu1.dcache.overall_accesses::total 155858549 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.077194 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.077194 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.100756 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.100756 # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.800804 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.800804 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120908 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120908 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106284 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106284 # miss rate for StoreCondReq accesses
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+system.cpu1.dcache.overall_miss_rate::total 0.092174 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15173.151331 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15173.151331 # average ReadReq miss latency
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+system.cpu1.dcache.WriteReq_avg_miss_latency::total 16716.934348 # average WriteReq miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14103.326712 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21288.642501 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21288.642501 # average StoreCondReq miss latency
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+system.cpu1.dcache.demand_avg_miss_latency::total 15998.960733 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15229.684111 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15229.684111 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 8615413 # number of cycles access was blocked
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+system.cpu1.dcache.blocked::no_mshrs 462301 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 741969 # number of cycles access was blocked
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+system.cpu1.dcache.fast_writes 535551 # number of fast writes performed
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+system.cpu1.dcache.writebacks::writebacks 3043634 # number of writebacks
+system.cpu1.dcache.writebacks::total 3043634 # number of writebacks
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+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1431846930 # number of LoadLockedReq MSHR miss cycles
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+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.008783 # average LoadLockedReq mshr miss latency
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+system.iocache.tags.tagsinuse 11.386738 # Cycle average of tags in use
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+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 101918.918919 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 170934.708179 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 170648.624356 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 69666.666667 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 69666.666667 # average WriteReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99500 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 170934.708179 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 170614.696047 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99500 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 170934.708179 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 170614.696047 # average overall mshr miss latency
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 14096 # number of quiesce instructions executed
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 4921 # number of quiesce instructions executed
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
+atags_addr=134217728
+boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
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+highest_el_is_64=false
+init_param=0
+kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel_addr_check=true
+load_addr_mask=268435455
+load_offset=2147483648
+machine_type=VExpress_EMM64
+mem_mode=timing
+mem_ranges=2147483648:2415919103
+memories=system.realview.nvmem system.physmem system.realview.vram
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+phys_addr_range_64=40
+readfile=/work/gem5.latest/tests/halt.sh
+reset_addr_64=0
+symbolfile=
+work_begin_ckpt_count=0
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+work_begin_exit_count=0
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+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.bridge]
+type=Bridge
+clk_domain=system.clk_domain
+delay=50000
+eventq_index=0
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
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+
+[system.cf0]
+type=IdeDisk
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+driveID=master
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+
+[system.cf0.image]
+type=CowDiskImage
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+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
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+image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
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+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=DerivO3CPU
+children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
+LFSTSize=1024
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+SQEntries=16
+SSITSize=1024
+activity=0
+backComSize=5
+branchPred=system.cpu.branchPred
+cachePorts=200
+checker=Null
+clk_domain=system.cpu_clk_domain
+commitToDecodeDelay=1
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+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
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+decodeToRenameDelay=2
+decodeWidth=3
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+do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
+dtb=system.cpu.dtb
+eventq_index=0
+fetchBufferSize=16
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+fetchToDecodeDelay=3
+fetchTrapLatency=1
+fetchWidth=3
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+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+iewToCommitDelay=1
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+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+issueToExecuteDelay=1
+issueWidth=8
+istage2_mmu=system.cpu.istage2_mmu
+itb=system.cpu.itb
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+max_insts_any_thread=0
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+needsTSO=false
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
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+numROBEntries=40
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+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
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+renameToROBDelay=1
+renameWidth=3
+simpoint_start_insts=
+smtCommitPolicy=RoundRobin
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+smtROBThreshold=100
+socket_id=0
+squashWidth=8
+store_set_clear_period=250000
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbWidth=8
+workload=
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=2048
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+RASSize=16
+choiceCtrBits=2
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+eventq_index=0
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+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=bi-mode
+
+[system.cpu.dcache]
+type=BaseCache
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+addr_ranges=0:18446744073709551615
+assoc=4
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+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
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+hit_latency=2
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+size=32768
+
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
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+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
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+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
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+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
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+
+[system.cpu.dtb]
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+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
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+sys=system
+port=system.cpu.toL2Bus.slave[3]
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
+eventq_index=0
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
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+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
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+
+[system.cpu.fuPool.FUList1]
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+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
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+
+[system.cpu.fuPool.FUList1.opList1]
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+[system.cpu.fuPool.FUList1.opList2]
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+
+[system.cpu.fuPool.FUList2.opList]
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+
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+
+[system.cpu.fuPool.FUList3.opList]
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+
+[system.cpu.fuPool.FUList4]
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+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
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+
+[system.cpu.fuPool.FUList4.opList00]
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+
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+[system.cpu.fuPool.FUList4.opList05]
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+[system.cpu.fuPool.FUList4.opList10]
+type=OpDesc
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+opClass=SimdSqrt
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+[system.cpu.fuPool.FUList4.opList11]
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+opLat=3
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+[system.cpu.fuPool.FUList4.opList16]
+type=OpDesc
+eventq_index=0
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+
+[system.cpu.fuPool.FUList4.opList17]
+type=OpDesc
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+
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+
+[system.cpu.fuPool.FUList4.opList19]
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+opLat=9
+
+[system.cpu.fuPool.FUList4.opList20]
+type=OpDesc
+eventq_index=0
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+[system.cpu.fuPool.FUList4.opList21]
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+opClass=FloatCmp
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+
+[system.cpu.fuPool.FUList4.opList22]
+type=OpDesc
+eventq_index=0
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+opClass=FloatCvt
+opLat=5
+
+[system.cpu.fuPool.FUList4.opList23]
+type=OpDesc
+eventq_index=0
+issueLat=9
+opClass=FloatDiv
+opLat=9
+
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
+eventq_index=0
+issueLat=33
+opClass=FloatSqrt
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+
+[system.cpu.fuPool.FUList4.opList25]
+type=OpDesc
+eventq_index=0
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+opClass=FloatMult
+opLat=4
+
+[system.cpu.icache]
+type=BaseCache
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+assoc=1
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+forward_snoops=true
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+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[4]
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+use_default_range=true
+width=8
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
+eventq_index=0
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=2147483648:2415919103
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
+tWTR=7500
+tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 09:18:22
+gem5 started Oct 29 2014 10:37:59
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu.isa: ISA system set to: 0x43dfb00 0x43dfb00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80080000
+info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 51557114994500 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 51.557115 # Number of seconds simulated
+sim_ticks 51557114994500 # Number of ticks simulated
+final_tick 51557114994500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 111994 # Simulator instruction rate (inst/s)
+host_op_rate 131638 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5181426993 # Simulator tick rate (ticks/s)
+host_mem_usage 668412 # Number of bytes of host memory used
+host_seconds 9950.37 # Real time elapsed on the host
+sim_insts 1114380469 # Number of instructions simulated
+sim_ops 1309844804 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.ide 437568 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 1002304 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 1237760 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 6145632 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 128560840 # Number of bytes read from this memory
+system.physmem.bytes_read::total 137384104 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 6145632 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 6145632 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 102180288 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 102783780 # Number of bytes written to this memory
+system.physmem.bytes_written::total 211790564 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 6837 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 15661 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 19340 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 111978 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2008776 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2162592 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1596567 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data 1608248 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 3311479 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 8487 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 19441 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 24008 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 119200 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2493562 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2664697 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 119200 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 119200 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1981885 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 132406 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1993591 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4107882 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1981885 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 140894 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 19441 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 24008 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 119200 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4487152 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6772580 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 2162592 # Number of read requests accepted
+system.physmem.writeReqs 3311479 # Number of write requests accepted
+system.physmem.readBursts 2162592 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 3311479 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 138204608 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 201280 # Total number of bytes read from write queue
+system.physmem.bytesWritten 207618304 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 137384104 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 211790564 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 3145 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 67428 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 48470 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 140382 # Per bank write bursts
+system.physmem.perBankRdBursts::1 139333 # Per bank write bursts
+system.physmem.perBankRdBursts::2 140658 # Per bank write bursts
+system.physmem.perBankRdBursts::3 133921 # Per bank write bursts
+system.physmem.perBankRdBursts::4 130324 # Per bank write bursts
+system.physmem.perBankRdBursts::5 134612 # Per bank write bursts
+system.physmem.perBankRdBursts::6 126217 # Per bank write bursts
+system.physmem.perBankRdBursts::7 133097 # Per bank write bursts
+system.physmem.perBankRdBursts::8 129592 # Per bank write bursts
+system.physmem.perBankRdBursts::9 157619 # Per bank write bursts
+system.physmem.perBankRdBursts::10 133394 # Per bank write bursts
+system.physmem.perBankRdBursts::11 133867 # Per bank write bursts
+system.physmem.perBankRdBursts::12 132326 # Per bank write bursts
+system.physmem.perBankRdBursts::13 132284 # Per bank write bursts
+system.physmem.perBankRdBursts::14 133117 # Per bank write bursts
+system.physmem.perBankRdBursts::15 128704 # Per bank write bursts
+system.physmem.perBankWrBursts::0 201659 # Per bank write bursts
+system.physmem.perBankWrBursts::1 203665 # Per bank write bursts
+system.physmem.perBankWrBursts::2 231223 # Per bank write bursts
+system.physmem.perBankWrBursts::3 188549 # Per bank write bursts
+system.physmem.perBankWrBursts::4 224931 # Per bank write bursts
+system.physmem.perBankWrBursts::5 188791 # Per bank write bursts
+system.physmem.perBankWrBursts::6 176287 # Per bank write bursts
+system.physmem.perBankWrBursts::7 226882 # Per bank write bursts
+system.physmem.perBankWrBursts::8 203233 # Per bank write bursts
+system.physmem.perBankWrBursts::9 233524 # Per bank write bursts
+system.physmem.perBankWrBursts::10 253232 # Per bank write bursts
+system.physmem.perBankWrBursts::11 198347 # Per bank write bursts
+system.physmem.perBankWrBursts::12 181957 # Per bank write bursts
+system.physmem.perBankWrBursts::13 175879 # Per bank write bursts
+system.physmem.perBankWrBursts::14 180282 # Per bank write bursts
+system.physmem.perBankWrBursts::15 175595 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 190 # Number of times write queue was full causing retry
+system.physmem.totGap 51557113761500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 13 # Read request sizes (log2)
+system.physmem.readPktSize::4 21272 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 2141307 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 1 # Write request sizes (log2)
+system.physmem.writePktSize::3 2572 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 3308906 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1296550 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 764534 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 68768 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 25837 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 916 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 532 # What read queue length does an incoming req see
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+system.physmem.wrQLenPdf::49 3461 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::53 2836 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 2345 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 2139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 1813 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 1591 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 1247 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::62 356 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 474 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 1034839 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 334.179783 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 188.532509 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 356.014667 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 392208 37.90% 37.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 234584 22.67% 60.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 87901 8.49% 69.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 49413 4.77% 73.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 38348 3.71% 77.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 26689 2.58% 80.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 21988 2.12% 82.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 25501 2.46% 84.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 158207 15.29% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1034839 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 135592 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 15.925969 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 128.724301 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 135587 100.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-43007 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 135592 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 135592 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 23.924981 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 20.930688 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 17.164557 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23 101303 74.71% 74.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31 7599 5.60% 80.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39 12845 9.47% 89.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47 3908 2.88% 92.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55 2324 1.71% 94.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63 925 0.68% 95.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71 2932 2.16% 97.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79 1250 0.92% 98.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87 889 0.66% 98.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95 249 0.18% 98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103 327 0.24% 99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111 193 0.14% 99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119 473 0.35% 99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127 16 0.01% 99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135 22 0.02% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143 28 0.02% 99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151 17 0.01% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159 31 0.02% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167 89 0.07% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175 56 0.04% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183 42 0.03% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191 7 0.01% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199 15 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207 2 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215 15 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223 3 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231 6 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239 3 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247 9 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255 5 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263 5 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271 3 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 135592 # Writes before turning the bus around for reads
+system.physmem.totQLat 43990891280 # Total ticks spent queuing
+system.physmem.totMemAccLat 84480522530 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 10797235000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 20371.37 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 39121.37 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.68 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2.66 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 4.11 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.05 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing
+system.physmem.readRowHits 1747291 # Number of row buffer hits during reads
+system.physmem.writeRowHits 2621349 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 80.91 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes
+system.physmem.avgGap 9418422.55 # Average gap between requests
+system.physmem.pageHitRate 80.85 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 49290195125250 # Time in different power states
+system.physmem.memoryStateTime::REF 1721605340000 # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem.memoryStateTime::ACT 545313634750 # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem.actEnergy::0 3951453240 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 3871929600 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 2156050875 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 2112660000 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 8412588600 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 8431020000 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 10640075760 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 10381277520 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 3367460045040 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 3367460045040 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 1383947967870 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 1368871606665 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 29720278968750 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 29733503847000 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 34496847150135 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 34494632385825 # Total energy per rank (pJ)
+system.physmem.averagePower::0 669.099654 # Core power per rank (mW)
+system.physmem.averagePower::1 669.056696 # Core power per rank (mW)
+system.membus.trans_dist::ReadReq 657217 # Transaction distribution
+system.membus.trans_dist::ReadResp 657217 # Transaction distribution
+system.membus.trans_dist::WriteReq 33865 # Transaction distribution
+system.membus.trans_dist::WriteResp 33865 # Transaction distribution
+system.membus.trans_dist::Writeback 1596567 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 1712339 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 1712339 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 48473 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 48476 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1541174 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1541174 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9221519 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9351669 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229018 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 229018 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 9580687 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 341910604 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 342081160 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264064 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7264064 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 349345224 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 2022 # Total snoops (count)
+system.membus.snoop_fanout::samples 5500895 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 5500895 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 5500895 # Request fanout histogram
+system.membus.reqLayer0.occupancy 109641999 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 5450500 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 32462148974 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer2.occupancy 21571101815 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer3.occupancy 186532342 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
+system.iobus.trans_dist::ReadReq 40379 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40379 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136716 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136733 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 17 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 354224 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7492654 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 981079506 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 179002658 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.branchPred.lookups 291488483 # Number of BP lookups
+system.cpu.branchPred.condPredicted 200150149 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 13608043 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 209143322 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 138326751 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 66.139693 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 37688944 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 403819 # Number of incorrect RAS predictions.
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 220000246 # DTB read hits
+system.cpu.dtb.read_misses 1007031 # DTB read misses
+system.cpu.dtb.write_hits 193886106 # DTB write hits
+system.cpu.dtb.write_misses 416122 # DTB write misses
+system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 63968 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 89690 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 112 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 15179 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 87251 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 221007277 # DTB read accesses
+system.cpu.dtb.write_accesses 194302228 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 413886352 # DTB hits
+system.cpu.dtb.misses 1423153 # DTB misses
+system.cpu.dtb.accesses 415309505 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 465588468 # ITB inst hits
+system.cpu.itb.inst_misses 176797 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 63968 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 63536 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 462381 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 465765265 # ITB inst accesses
+system.cpu.itb.hits 465588468 # DTB hits
+system.cpu.itb.misses 176797 # DTB misses
+system.cpu.itb.accesses 465765265 # DTB accesses
+system.cpu.numCycles 2146849645 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.fetch.icacheStallCycles 791511347 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1301628389 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 291488483 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 176015695 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 1268750537 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 29307286 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 4254748 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 27926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 12217982 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 1219824 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 381 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 465107423 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 6746831 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 53918 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 2092636388 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.729302 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.142136 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 1367675983 65.36% 65.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 280886167 13.42% 78.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 86945610 4.15% 82.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 357128628 17.07% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 2092636388 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.135775 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.606297 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 614820490 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 852644163 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 531180111 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 83391963 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 10599661 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 41490545 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 4112846 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 1415541998 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 32718079 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 10599661 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 678805488 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 83662136 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 556428904 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 549849830 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 213290369 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 1391734034 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 7977079 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 7435136 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 893230 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 1023922 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 127479585 # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents 25199 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 1342075875 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2217645602 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1652184740 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1639045 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 1263873564 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 78202308 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 44203192 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 39719264 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 172796539 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 223511224 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 198396121 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 12647992 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 11061331 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1338396177 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 44508712 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1370133902 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 4153047 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 65240654 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 41320787 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 373617 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 2092636388 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.654741 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 0.915536 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 1237717942 59.15% 59.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 455529583 21.77% 80.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 292996726 14.00% 94.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 96986296 4.63% 99.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 9377226 0.45% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 28615 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 2092636388 # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 74528454 34.28% 34.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 90672 0.04% 34.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 26772 0.01% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 287 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 58830485 27.06% 61.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 83911289 38.60% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 945793660 69.03% 69.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2946266 0.22% 69.24% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 129775 0.01% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 114397 0.01% 69.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 224851656 16.41% 85.67% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 196298100 14.33% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total 1370133902 # Type of FU issued
+system.cpu.iq.rate 0.638207 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 217387959 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.158662 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5052021388 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 1447405501 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1347303683 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 2423809 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 923681 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 885699 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1585997449 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 1524411 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 5766333 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads 16996131 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 24128 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 185382 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 8259714 # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads 3623609 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 3385962 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles 10599661 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 11961718 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 7304667 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1383179145 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 223511224 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 198396121 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 39177517 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 185228 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 6936317 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 185382 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4274350 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 5730421 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 10004771 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1356817685 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 220004444 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 11924579 # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp 0 # number of swp insts executed
+system.cpu.iew.exec_nop 274256 # number of nop insts executed
+system.cpu.iew.exec_refs 413901554 # number of memory reference insts executed
+system.cpu.iew.exec_branches 257473473 # Number of branches executed
+system.cpu.iew.exec_stores 193897110 # Number of stores executed
+system.cpu.iew.exec_rate 0.632004 # Inst execution rate
+system.cpu.iew.wb_sent 1349182874 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1348189382 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 579023420 # num instructions producing a value
+system.cpu.iew.wb_consumers 949767765 # num instructions consuming a value
+system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate 0.627985 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.609647 # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitSquashedInsts 62443917 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 44135095 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 9554061 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 2078483160 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.630193 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.269789 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 1396354428 67.18% 67.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 397736022 19.14% 86.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 152396085 7.33% 93.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 44287772 2.13% 95.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 35996912 1.73% 97.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 18656723 0.90% 98.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 10905184 0.52% 98.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 5449343 0.26% 99.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 16700691 0.80% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 2078483160 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 1114380469 # Number of instructions committed
+system.cpu.commit.committedOps 1309844804 # Number of ops (including micro ops) committed
+system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.refs 396651499 # Number of memory references committed
+system.cpu.commit.loads 206515092 # Number of loads committed
+system.cpu.commit.membars 9189565 # Number of memory barriers committed
+system.cpu.commit.branches 249089949 # Number of branches committed
+system.cpu.commit.fp_insts 873640 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 1196978104 # Number of committed integer instructions.
+system.cpu.commit.function_calls 31078874 # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 910428363 69.51% 69.51% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 2554988 0.20% 69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 104143 0.01% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 105769 0.01% 69.72% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.72% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.72% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.72% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 206515092 15.77% 85.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 190136407 14.52% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total 1309844804 # Class of committed instruction
+system.cpu.commit.bw_lim_events 16700691 # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads 3424556806 # The number of ROB reads
+system.cpu.rob.rob_writes 2758622493 # The number of ROB writes
+system.cpu.timesIdled 9031521 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 54213257 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 100967380384 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 1114380469 # Number of Instructions Simulated
+system.cpu.committedOps 1309844804 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 1.926496 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.926496 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.519077 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.519077 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1611998606 # number of integer regfile reads
+system.cpu.int_regfile_writes 948639021 # number of integer regfile writes
+system.cpu.fp_regfile_reads 1420015 # number of floating regfile reads
+system.cpu.fp_regfile_writes 765124 # number of floating regfile writes
+system.cpu.cc_regfile_reads 315259155 # number of cc regfile reads
+system.cpu.cc_regfile_writes 316098925 # number of cc regfile writes
+system.cpu.misc_regfile_reads 6952427793 # number of misc regfile reads
+system.cpu.misc_regfile_writes 45059384 # number of misc regfile writes
+system.cpu.toL2Bus.trans_dist::ReadReq 28539920 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 28531649 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 33865 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 33865 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 9369509 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1712344 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1605675 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 61529 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 61535 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 3074731 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 3074731 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33703094 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 37825776 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 810571 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3115869 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 75455310 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1077469744 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1502191576 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2724416 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10868120 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 2593253856 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 644632 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 42703026 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5.002705 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.051942 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 42587504 99.73% 99.73% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 115522 0.27% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 42703026 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 32333793873 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy 871500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 25296093441 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 19876823538 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy 472614279 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy 1760067316 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu.icache.tags.replacements 16829629 # number of replacements
+system.cpu.icache.tags.tagsinuse 511.959617 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 447510611 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 16830141 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 26.589831 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 12236526000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 511.959617 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.999921 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 291 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 481916487 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 481916487 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 447510611 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 447510611 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 447510611 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 447510611 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 447510611 # number of overall hits
+system.cpu.icache.overall_hits::total 447510611 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 17575514 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 17575514 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 17575514 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 17575514 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 17575514 # number of overall misses
+system.cpu.icache.overall_misses::total 17575514 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 231527181766 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 231527181766 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 231527181766 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 231527181766 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 231527181766 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 231527181766 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 465086125 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 465086125 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 465086125 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 465086125 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 465086125 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 465086125 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.037790 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.037790 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.037790 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.037790 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.037790 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.037790 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13173.280836 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13173.280836 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13173.280836 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13173.280836 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13173.280836 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13173.280836 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 11084 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 920 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 12.047826 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 745151 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 745151 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 745151 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 745151 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 745151 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 745151 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16830363 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 16830363 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 16830363 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 16830363 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 16830363 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 16830363 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191394786019 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 191394786019 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191394786019 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 191394786019 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191394786019 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 191394786019 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1413030250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1413030250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1413030250 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total 1413030250 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036188 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036188 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036188 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.036188 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036188 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.036188 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11371.993939 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11371.993939 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11371.993939 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11371.993939 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11371.993939 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11371.993939 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.tags.replacements 1866229 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 64521.528187 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 35312731 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 1928499 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 18.310993 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 13813873928000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 34323.724648 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 307.320059 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 449.834309 # Average occupied blocks per requestor
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005390 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.160841 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.068825 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011528 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.056790 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005390 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.160841 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.068825 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 66907.205670 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66214.178335 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64286.978734 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69004.344071 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68136.808705 # average ReadReq mshr miss latency
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+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10006.580745 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10006.580745 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71012.621808 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71012.621808 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 66907.205670 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66214.178335 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64286.978734 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70545.291099 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70213.494723 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 66907.205670 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66214.178335 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64286.978734 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70545.291099 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70213.494723 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
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+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.dcache.tags.tagsinuse 511.985330 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 363427258 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 13757396 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 26.416864 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 1485814250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.985330 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999971 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999971 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 382 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 1609448196 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1609448196 # Number of data accesses
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+system.cpu.dcache.ReadReq_hits::total 188132338 # number of ReadReq hits
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+system.cpu.dcache.ReadReq_misses::total 12712279 # number of ReadReq misses
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+system.cpu.dcache.StoreCondReq_miss_latency::total 117003 # number of StoreCondReq miss cycles
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+system.cpu.dcache.overall_miss_latency::total 1225081776243 # number of overall miss cycles
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+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.101960 # miss rate for LoadLockedReq accesses
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+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
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+system.cpu.dcache.overall_miss_rate::total 0.087311 # miss rate for overall accesses
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+system.cpu.dcache.ReadReq_avg_miss_latency::total 16000.556505 # average ReadReq miss latency
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+system.cpu.dcache.WriteReq_avg_miss_latency::total 53861.197196 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15672.030311 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15672.030311 # average LoadLockedReq miss latency
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+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500.500000 # average StoreCondReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 38669.285110 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 36295.361841 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 36295.361841 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 38319499 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2284719 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.772084 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 1605675 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 9369509 # number of writebacks
+system.cpu.dcache.writebacks::total 9369509 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5628309 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 5628309 # number of ReadReq MSHR hits
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+system.cpu.dcache.WriteReq_mshr_hits::total 15829986 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 265840 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 265840 # number of LoadLockedReq MSHR hits
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+system.cpu.dcache.demand_mshr_hits::total 21458295 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 21458295 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 21458295 # number of overall MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses::total 7083970 # number of ReadReq MSHR misses
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+system.cpu.dcache.WriteReq_mshr_misses::total 3120649 # number of WriteReq MSHR misses
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+system.cpu.dcache.SoftPFReq_mshr_misses::total 2065320 # number of SoftPFReq MSHR misses
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+system.cpu.dcache.LoadLockedReq_mshr_misses::total 284579 # number of LoadLockedReq MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total 12269939 # number of overall MSHR misses
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+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 31611668497 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 31611668497 # number of SoftPFReq MSHR miss cycles
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+system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 59007365277 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3751055249 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3751055249 # number of LoadLockedReq MSHR miss cycles
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+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 104997 # number of StoreCondReq MSHR miss cycles
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+system.cpu.dcache.demand_mshr_miss_latency::total 250741484767 # number of demand (read+write) MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::total 282353153264 # number of overall MSHR miss cycles
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+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5729434750 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5587276983 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5587276983 # number of WriteReq MSHR uncacheable cycles
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+system.cpu.dcache.overall_mshr_uncacheable_latency::total 11316711733 # number of overall MSHR uncacheable cycles
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+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035271 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.017034 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.017034 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813798 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813798 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052716 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052716 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
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+system.cpu.dcache.demand_mshr_miss_rate::total 0.026571 # mshr miss rate for demand accesses
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+system.cpu.dcache.overall_mshr_miss_rate::total 0.031739 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14466.142272 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14466.142272 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47510.555303 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47510.555303 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15305.942177 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15305.942177 # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data inf # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13181.068347 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13181.068347 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17499.500000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17499.500000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24571.371530 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24571.371530 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23011.781335 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23011.781335 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.tags.replacements 115458 # number of replacements
+system.iocache.tags.tagsinuse 10.450727 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 13090278324000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.528058 # Average occupied blocks per requestor
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+system.iocache.tags.occ_percent::realview.ide 0.432667 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.653170 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 1039786 # Number of tag accesses
+system.iocache.tags.data_accesses 1039786 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses
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+system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
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+system.iocache.WriteInvalidateReq_misses::total 17 # number of WriteInvalidateReq misses
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+system.iocache.ReadReq_miss_latency::realview.ide 1929395843 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 1934942843 # number of ReadReq miss cycles
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+system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles
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+system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses)
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+system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
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+system.iocache.ReadReq_avg_miss_latency::realview.ide 218926.114036 # average ReadReq miss latency
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+system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency
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+system.iocache.demand_avg_miss_latency::realview.ide 218926.114036 # average overall miss latency
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+system.iocache.overall_avg_miss_latency::realview.ide 218926.114036 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 218601.812154 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 53350 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked
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+system.iocache.avg_blocked_cycles::no_mshrs 9.717668 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 106664 # number of fast writes performed
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+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6546677301 # number of WriteInvalidateReq MSHR miss cycles
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+system.iocache.demand_mshr_miss_latency::realview.ide 1470987863 # number of demand (read+write) MSHR miss cycles
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+system.iocache.overall_mshr_miss_latency::realview.ide 1470987863 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 1474793863 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
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+system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
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+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
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+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
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+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166911.138432 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 166622.696384 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
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+system.iocache.demand_avg_mshr_miss_latency::realview.ide 166911.138432 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 166586.904213 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 95150 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 166911.138432 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 166586.904213 # average overall mshr miss latency
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.quiesce 17164 # number of quiesce instructions executed
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
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+boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
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+early_kernel_symbols=false
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+highest_el_is_64=false
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+kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel_addr_check=true
+load_addr_mask=268435455
+load_offset=2147483648
+machine_type=VExpress_EMM64
+mem_mode=atomic
+mem_ranges=2147483648:2415919103
+memories=system.realview.vram system.physmem system.realview.nvmem
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+phys_addr_range_64=40
+readfile=/work/gem5.latest/tests/halt.sh
+reset_addr_64=0
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.bridge]
+type=Bridge
+clk_domain=system.clk_domain
+delay=50000
+eventq_index=0
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+eventq_index=0
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+eventq_index=0
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+eventq_index=0
+image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu0]
+type=AtomicSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu0.dstage2_mmu
+dtb=system.cpu0.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+istage2_mmu=system.cpu0.istage2_mmu
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+width=1
+workload=
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+eventq_index=0
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+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
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+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
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+sequential_access=false
+size=32768
+
+[system.cpu0.dstage2_mmu]
+type=ArmStage2MMU
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+eventq_index=0
+stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+tlb=system.cpu0.dtb
+
+[system.cpu0.dstage2_mmu.stage2_tlb]
+type=ArmTLB
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+walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu0.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[5]
+
+[system.cpu0.dtb]
+type=ArmTLB
+children=walker
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+is_stage2=false
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[3]
+
+[system.cpu0.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=1
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu0.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu0.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
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+id_aa64isar0_el1=0
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+id_aa64mmfr0_el1=15728642
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+id_aa64pfr0_el1=17
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+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu0.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+tlb=system.cpu0.itb
+
+[system.cpu0.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
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+is_stage2=true
+size=32
+walker=system.cpu0.istage2_mmu.stage2_tlb.walker
+
+[system.cpu0.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[4]
+
+[system.cpu0.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu0.itb.walker
+
+[system.cpu0.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[2]
+
+[system.cpu0.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu1]
+type=TimingSimpleCPU
+children=dstage2_mmu dtb isa istage2_mmu itb tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
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+dstage2_mmu=system.cpu1.dstage2_mmu
+dtb=system.cpu1.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=Null
+isa=system.cpu1.isa
+istage2_mmu=system.cpu1.istage2_mmu
+itb=system.cpu1.itb
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+
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+
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+
+[system.cpu1.isa]
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+
+[system.cpu1.istage2_mmu]
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+
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+
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+[system.cpu1.itb.walker]
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+
+[system.cpu1.tracer]
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+
+[system.cpu2]
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+branchPred=system.cpu2.branchPred
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+workload=
+
+[system.cpu2.branchPred]
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+
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+[system.cpu2.dtb.walker]
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+
+[system.cpu2.fuPool]
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+FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
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+
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+count=4
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+
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+[system.cpu2.fuPool.FUList6.opList]
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+[system.cpu2.fuPool.FUList7]
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+[system.cpu2.fuPool.FUList7.opList0]
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+[system.cpu2.fuPool.FUList8]
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+
+[system.cpu2.fuPool.FUList8.opList]
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+opLat=3
+
+[system.cpu2.isa]
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+midr=1091551472
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+
+[system.cpu2.istage2_mmu]
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+
+[system.cpu2.istage2_mmu.stage2_tlb]
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+
+[system.cpu2.istage2_mmu.stage2_tlb.walker]
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+[system.cpu2.itb]
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+[system.cpu2.itb.walker]
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+
+[system.cpu2.tracer]
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+
+[system.cpu_clk_domain]
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+domain_id=-1
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+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
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+transition_latency=100000000
+
+[system.intrctrl]
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+
+[system.iobus]
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+clk_domain=system.clk_domain
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+header_cycles=1
+use_default_range=true
+width=8
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
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+system=system
+tags=system.iocache.tags
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+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
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+[system.l2c]
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+system=system
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+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.l2c.tags]
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+size=4194304
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=2147483648:2415919103
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
+tWTR=7500
+tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 09:18:22
+gem5 started Oct 29 2014 11:58:52
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+ 0: system.cpu0.isa: ISA system set to: 0x563eb00 0x563eb00
+ 0: system.cpu1.isa: ISA system set to: 0x563eb00 0x563eb00
+ 0: system.cpu2.isa: ISA system set to: 0x563eb00 0x563eb00
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 51.274675 # Number of seconds simulated
+sim_ticks 51274674635500 # Number of ticks simulated
+final_tick 51274674635500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 308954 # Simulator instruction rate (inst/s)
+host_op_rate 363040 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 18009090527 # Simulator tick rate (ticks/s)
+host_mem_usage 661116 # Number of bytes of host memory used
+host_seconds 2847.16 # Real time elapsed on the host
+sim_insts 879639951 # Number of instructions simulated
+sim_ops 1033631621 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::realview.ide 391104 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 245504 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 412480 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 2683060 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 32648008 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 82560 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 137216 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 615744 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 8957184 # Number of bytes read from this memory
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+system.physmem.bytes_read::cpu2.itb.walker 332480 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 2079744 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 22931008 # Number of bytes read from this memory
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+system.physmem.bytes_inst_read::cpu0.inst 2683060 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 615744 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 2079744 # Number of instructions bytes read from this memory
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+system.physmem.bytes_written::writebacks 40940416 # Number of bytes written to this memory
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+system.physmem.num_reads::cpu0.dtb.walker 3836 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 6445 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 82330 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 510138 # Number of read requests responded to by this memory
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+system.physmem.num_writes::total 2312870 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 7628 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 4788 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::cpu2.dtb.walker 4123 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_inst_read::total 104897 # Instruction read bandwidth from this memory (bytes/s)
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+system.physmem.bw_write::total 2884067 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bw_total::cpu0.inst 52327 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::cpu1.dtb.walker 1610 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 2676 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 12009 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 419512 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 4123 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.itb.walker 6484 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 40561 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 1003555 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4282954 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 556099 # Number of read requests accepted
+system.physmem.writeReqs 996967 # Number of write requests accepted
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+system.physmem.writeBursts 996967 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 35500160 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 90176 # Total number of bytes read from write queue
+system.physmem.bytesWritten 61170112 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 35590336 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 63805888 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 1409 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 41184 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 18778 # Number of requests that are neither read nor write
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+system.physmem.perBankRdBursts::3 34663 # Per bank write bursts
+system.physmem.perBankRdBursts::4 34185 # Per bank write bursts
+system.physmem.perBankRdBursts::5 37826 # Per bank write bursts
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+system.physmem.perBankRdBursts::13 34396 # Per bank write bursts
+system.physmem.perBankRdBursts::14 33124 # Per bank write bursts
+system.physmem.perBankRdBursts::15 31854 # Per bank write bursts
+system.physmem.perBankWrBursts::0 51538 # Per bank write bursts
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+system.physmem.perBankWrBursts::4 72819 # Per bank write bursts
+system.physmem.perBankWrBursts::5 60009 # Per bank write bursts
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+system.physmem.perBankWrBursts::9 79578 # Per bank write bursts
+system.physmem.perBankWrBursts::10 79171 # Per bank write bursts
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+system.physmem.perBankWrBursts::12 53518 # Per bank write bursts
+system.physmem.perBankWrBursts::13 50714 # Per bank write bursts
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+system.physmem.numWrRetry 45 # Number of times write queue was full causing retry
+system.physmem.totGap 51273477930500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
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+system.physmem.readPktSize::2 0 # Read request sizes (log2)
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+system.physmem.readPktSize::5 0 # Read request sizes (log2)
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+system.physmem.writePktSize::0 0 # Write request sizes (log2)
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+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 996967 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 389698 # What read queue length does an incoming req see
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+system.physmem.wrQLenPdf::58 238 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::62 89 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 114 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 313965 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 307.901429 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 171.041097 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 348.087880 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 132720 42.27% 42.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 70601 22.49% 64.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 25843 8.23% 72.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 12745 4.06% 77.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 9334 2.97% 80.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 6247 1.99% 82.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 5388 1.72% 83.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 6641 2.12% 85.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 44446 14.16% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 313965 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 40272 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 13.773590 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 142.393884 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 40271 100.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::27648-28671 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 40272 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 40272 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 23.733189 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 21.769670 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 12.088668 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3 6 0.01% 0.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7 2 0.00% 0.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11 4 0.01% 0.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15 68 0.17% 0.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 21743 53.99% 54.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 7529 18.70% 72.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 844 2.10% 74.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 2202 5.47% 80.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 3572 8.87% 89.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 961 2.39% 91.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 568 1.41% 93.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 548 1.36% 94.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 664 1.65% 96.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 107 0.27% 96.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 86 0.21% 96.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 131 0.33% 96.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 645 1.60% 98.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 191 0.47% 99.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 148 0.37% 99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 110 0.27% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 71 0.18% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 17 0.04% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 8 0.02% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 9 0.02% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 6 0.01% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 4 0.01% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 5 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 6 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 4 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 5 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 40272 # Writes before turning the bus around for reads
+system.physmem.totQLat 10784853014 # Total ticks spent queuing
+system.physmem.totMemAccLat 21185290514 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2773450000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 19443.03 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 38193.03 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 0.69 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 0.69 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.24 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.01 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 21.80 # Average write queue length when enqueuing
+system.physmem.readRowHits 423817 # Number of row buffer hits during reads
+system.physmem.writeRowHits 772691 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 76.41 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 80.84 # Row buffer hit rate for writes
+system.physmem.avgGap 33014358.65 # Average gap between requests
+system.physmem.pageHitRate 79.21 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 49344562776500 # Time in different power states
+system.physmem.memoryStateTime::REF 1712173840000 # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem.memoryStateTime::ACT 217931188500 # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem.actEnergy::0 1214869320 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 1158706080 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 662875125 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 632230500 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 2186223000 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 2140359000 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 3087655200 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 3105818640 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 3349012031040 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 3349012031040 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 1215657712530 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 1211135236200 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 29698434260250 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 29702401344750 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 34270255626465 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 34269585726210 # Total energy per rank (pJ)
+system.physmem.averagePower::0 668.366215 # Core power per rank (mW)
+system.physmem.averagePower::1 668.353150 # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 512200 # Transaction distribution
+system.membus.trans_dist::ReadResp 512200 # Transaction distribution
+system.membus.trans_dist::WriteReq 33772 # Transaction distribution
+system.membus.trans_dist::WriteResp 33772 # Transaction distribution
+system.membus.trans_dist::Writeback 639694 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 1670603 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 1670603 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 36363 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 36366 # Transaction distribution
+system.membus.trans_dist::ReadExReq 685391 # Transaction distribution
+system.membus.trans_dist::ReadExResp 685391 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122952 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6750 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6155552 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 6285312 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229159 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 229159 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 6514471 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156082 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13500 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 212389664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 212559378 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7272512 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7272512 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 219831890 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 1887 # Total snoops (count)
+system.membus.snoop_fanout::samples 3467502 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3467502 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 3467502 # Request fanout histogram
+system.membus.reqLayer0.occupancy 48925999 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 1640000 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 9861261476 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 6001066379 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer3.occupancy 87450398 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.l2c.tags.replacements 829792 # number of replacements
+system.l2c.tags.tagsinuse 64538.969055 # Cycle average of tags in use
+system.l2c.tags.total_refs 28099922 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 891020 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 31.536803 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 13806560382000 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 35856.169681 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker 191.429036 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker 290.837170 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 3857.675402 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 9456.283942 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker 48.759094 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker 73.219747 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 709.055197 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 2692.383155 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker 111.816270 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.itb.walker 164.499208 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst 2725.095268 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data 8361.745885 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.547122 # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::total 0.984787 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023 502 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024 60726 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4 489 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 2207 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3 4867 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4 53302 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023 0.007660 # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024 0.926605 # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses 265686556 # Number of tag accesses
+system.l2c.tags.data_accesses 265686556 # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker 200882 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 128104 # number of ReadReq hits
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+system.l2c.ReadReq_hits::cpu0.data 3104423 # number of ReadReq hits
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+system.l2c.ReadReq_hits::cpu2.data 2406989 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 21853354 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 6807908 # number of Writeback hits
+system.l2c.Writeback_hits::total 6807908 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 5076 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 1634 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data 4357 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 11067 # number of UpgradeReq hits
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+system.l2c.demand_hits::cpu2.data 2890652 # number of demand (read+write) hits
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+system.l2c.overall_hits::total 23256328 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker 3836 # number of ReadReq misses
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+system.l2c.ReadReq_misses::cpu1.data 42836 # number of ReadReq misses
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+system.l2c.ReadReq_misses::cpu2.itb.walker 5220 # number of ReadReq misses
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+system.l2c.ReadReq_misses::cpu2.data 126310 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 426584 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 17268 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 5409 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data 13103 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 35780 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu2.data 2 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
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+system.l2c.ReadExReq_misses::cpu1.data 97202 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data 232172 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 685971 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker 3836 # number of demand (read+write) misses
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1618942500 # number of ReadReq MSHR uncacheable cycles
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+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 835101000 # number of WriteReq MSHR uncacheable cycles
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+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.042827 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.004693 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.042141 # mshr miss rate for ReadReq accesses
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.767997 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.750458 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.395159 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.400000 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
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+system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.035732 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005614 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data 0.110330 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.022675 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 63706.007752 # average ReadReq mshr miss latency
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61167.004469 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61511.345597 # average ReadReq mshr miss latency
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65805.130755 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 70136.036427 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 67215.681681 # average ReadReq mshr miss latency
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10023.131191 # average UpgradeReq mshr miss latency
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+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59652.855525 # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73786.183105 # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65805.130755 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73786.183105 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 69336.318663 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
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+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
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+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq 22792948 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 22787515 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 33772 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 33772 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 6807908 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 1600102 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 1563939 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 46847 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 46853 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 2088945 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 2088945 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 29041280 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27958653 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 843900 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1753644 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 59597477 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 926729300 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1105413310 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3095064 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6286720 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 2041524394 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 368391 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 33333670 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 5.003466 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.058768 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 33218144 99.65% 99.65% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 115526 0.35% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 33333670 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 25204206978 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 1129500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 35295410102 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 21026275011 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 267100118 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 646797339 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 40334 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40334 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136600 # Transaction distribution
+system.iobus.trans_dist::WriteResp 66161 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 65 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 70504 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48070 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122952 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230966 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230966 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353998 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48090 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 156082 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334296 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334296 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7492464 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 17794000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 2000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 9530000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 91000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 16563000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 71000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 339092871 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 44416000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 84714602 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer4.occupancy 144000 # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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+system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 79163453 # DTB read hits
+system.cpu0.dtb.read_misses 85617 # DTB read misses
+system.cpu0.dtb.write_hits 72660708 # DTB write hits
+system.cpu0.dtb.write_misses 28291 # DTB write misses
+system.cpu0.dtb.flush_tlb 1291 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 21000 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 522 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 52340 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 3792 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 9968 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 79249070 # DTB read accesses
+system.cpu0.dtb.write_accesses 72688999 # DTB write accesses
+system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dtb.hits 151824161 # DTB hits
+system.cpu0.dtb.misses 113908 # DTB misses
+system.cpu0.dtb.accesses 151938069 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.inst_hits 424925918 # ITB inst hits
+system.cpu0.itb.inst_misses 64800 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.flush_tlb 1291 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 21000 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 522 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 37053 # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.inst_accesses 424990718 # ITB inst accesses
+system.cpu0.itb.hits 424925918 # DTB hits
+system.cpu0.itb.misses 64800 # DTB misses
+system.cpu0.itb.accesses 424990718 # DTB accesses
+system.cpu0.numCycles 511314689 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.committedInsts 424739937 # Number of instructions committed
+system.cpu0.committedOps 499770936 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 458702697 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 419703 # Number of float alu accesses
+system.cpu0.num_func_calls 25504192 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 64716286 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 458702697 # number of integer instructions
+system.cpu0.num_fp_insts 419703 # number of float instructions
+system.cpu0.num_int_register_reads 675611920 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 364415309 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 677474 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 352628 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 112049346 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 111774000 # number of times the CC registers were written
+system.cpu0.num_mem_refs 151917751 # number of memory refs
+system.cpu0.num_load_insts 79236622 # Number of load instructions
+system.cpu0.num_store_insts 72681129 # Number of store instructions
+system.cpu0.num_idle_cycles 499253695.584872 # Number of idle cycles
+system.cpu0.num_busy_cycles 12060993.415128 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.023588 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.976412 # Percentage of idle cycles
+system.cpu0.Branches 94879530 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 346985072 69.39% 69.39% # Class of executed instruction
+system.cpu0.op_class::IntMult 1058214 0.21% 69.60% # Class of executed instruction
+system.cpu0.op_class::IntDiv 47254 0.01% 69.61% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 51204 0.01% 69.62% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 69.62% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.62% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.62% # Class of executed instruction
+system.cpu0.op_class::MemRead 79236622 15.85% 85.47% # Class of executed instruction
+system.cpu0.op_class::MemWrite 72681129 14.53% 100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu0.op_class::total 500059496 # Class of executed instruction
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 16293 # number of quiesce instructions executed
+system.cpu0.icache.tags.replacements 14476947 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.977197 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 610391871 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 14477459 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 42.161533 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 8950087250 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 497.229242 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 6.558404 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst 8.189551 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.971151 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst 0.012809 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst 0.015995 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses 639762187 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 639762187 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 418346381 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 129402990 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst 62642500 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 610391871 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 418346381 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst 129402990 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst 62642500 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 610391871 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 418346381 # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst 129402990 # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst 62642500 # number of overall hits
+system.cpu0.icache.overall_hits::total 610391871 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 6638991 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst 2049875 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst 6203870 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 14892736 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 6638991 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst 2049875 # number of demand (read+write) misses
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+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.072087 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.155353 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.096390 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000002 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000004 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024623 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024613 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data 0.076331 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.044187 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028751 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028592 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data 0.079775 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.048028 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15634.153265 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17928.852925 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 12009.788963 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32950.033492 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 41332.674077 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 32977.846451 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14009.897990 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14111.273145 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9874.101985 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26501 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 18000.400000 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 19417.166667 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20606.164768 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 29197.542864 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 20773.860794 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17643.344690 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 27796.392655 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 19010.229050 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 21434212 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 26746 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 1267990 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 380 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.904086 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 70.384211 # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes 1563939 # number of fast writes performed
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks 6807908 # number of writebacks
+system.cpu0.dcache.writebacks::total 6807908 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 948 # number of ReadReq MSHR hits
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+system.cpu0.dcache.ReadReq_mshr_hits::total 2611251 # number of ReadReq MSHR hits
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+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 3551132 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 3555492 # number of WriteReq MSHR hits
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+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 136103 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 146070 # number of LoadLockedReq MSHR hits
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+system.cpu0.dcache.demand_mshr_hits::cpu2.data 6161435 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 6166743 # number of demand (read+write) MSHR hits
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+system.cpu0.dcache.overall_mshr_hits::total 6166743 # number of overall MSHR hits
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+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 441899 # number of SoftPFReq MSHR misses
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+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 11879826672 # number of SoftPFReq MSHR miss cycles
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+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu2.data 16470207883 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 22843163883 # number of WriteInvalidateReq MSHR miss cycles
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 1117052111 # number of LoadLockedReq MSHR miss cycles
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+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 79998 # number of StoreCondReq MSHR miss cycles
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+system.cpu0.dcache.demand_mshr_miss_latency::total 79945793292 # number of demand (read+write) MSHR miss cycles
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+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 959248000 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2705203500 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2654869958 # number of WriteReq MSHR uncacheable cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5360073458 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033155 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031740 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017120 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014787 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013648 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007228 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.766157 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.748749 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.380083 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055654 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.060930 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.030674 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000002 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000004 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024496 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023456 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.012480 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028474 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027106 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.014444 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13564.597042 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15408.779055 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14885.547139 # average ReadReq mshr miss latency
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+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 39001.498893 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36558.411875 # average WriteReq mshr miss latency
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+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20612.346762 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18875.263625 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data inf # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12049.534870 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12718.922768 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12533.082012 # average LoadLockedReq mshr miss latency
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+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 15999.600000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 17416.166667 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18505.722380 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21694.423549 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20773.391119 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17968.167892 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21543.997771 # average overall mshr miss latency
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+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.inst_hits 0 # ITB inst hits
+system.cpu1.dtb.inst_misses 0 # ITB inst misses
+system.cpu1.dtb.read_hits 24842678 # DTB read hits
+system.cpu1.dtb.read_misses 30288 # DTB read misses
+system.cpu1.dtb.write_hits 22204387 # DTB write hits
+system.cpu1.dtb.write_misses 9453 # DTB write misses
+system.cpu1.dtb.flush_tlb 1282 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 6426 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 146 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 22120 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 1240 # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults 2953 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 24872966 # DTB read accesses
+system.cpu1.dtb.write_accesses 22213840 # DTB write accesses
+system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dtb.hits 47047065 # DTB hits
+system.cpu1.dtb.misses 39741 # DTB misses
+system.cpu1.dtb.accesses 47086806 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.inst_hits 131452865 # ITB inst hits
+system.cpu1.itb.inst_misses 23431 # ITB inst misses
+system.cpu1.itb.read_hits 0 # DTB read hits
+system.cpu1.itb.read_misses 0 # DTB read misses
+system.cpu1.itb.write_hits 0 # DTB write hits
+system.cpu1.itb.write_misses 0 # DTB write misses
+system.cpu1.itb.flush_tlb 1282 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 6426 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 146 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 16167 # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses 0 # DTB read accesses
+system.cpu1.itb.write_accesses 0 # DTB write accesses
+system.cpu1.itb.inst_accesses 131476296 # ITB inst accesses
+system.cpu1.itb.hits 131452865 # DTB hits
+system.cpu1.itb.misses 23431 # DTB misses
+system.cpu1.itb.accesses 131476296 # DTB accesses
+system.cpu1.numCycles 1282114185 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.committedInsts 131358204 # Number of instructions committed
+system.cpu1.committedOps 154205938 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 141499337 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 128756 # Number of float alu accesses
+system.cpu1.num_func_calls 7727196 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 20146536 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 141499337 # number of integer instructions
+system.cpu1.num_fp_insts 128756 # number of float instructions
+system.cpu1.num_int_register_reads 205950168 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 112374883 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 204901 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 115300 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 34581843 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 34518712 # number of times the CC registers were written
+system.cpu1.num_mem_refs 47044288 # number of memory refs
+system.cpu1.num_load_insts 24842081 # Number of load instructions
+system.cpu1.num_store_insts 22202207 # Number of store instructions
+system.cpu1.num_idle_cycles 1255604442.364680 # Number of idle cycles
+system.cpu1.num_busy_cycles 26509742.635320 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.020677 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.979323 # Percentage of idle cycles
+system.cpu1.Branches 29364446 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 106871098 69.26% 69.26% # Class of executed instruction
+system.cpu1.op_class::IntMult 352774 0.23% 69.49% # Class of executed instruction
+system.cpu1.op_class::IntDiv 14834 0.01% 69.50% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 17563 0.01% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::MemRead 24842081 16.10% 85.61% # Class of executed instruction
+system.cpu1.op_class::MemWrite 22202207 14.39% 100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::total 154300599 # Class of executed instruction
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.cpu2.branchPred.lookups 95476448 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 64928073 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 4299413 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 64784895 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 46332623 # Number of BTB hits
+system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu2.branchPred.BTBHitPct 71.517632 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 12285804 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 131917 # Number of incorrect RAS predictions.
+system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu2.dtb.inst_hits 0 # ITB inst hits
+system.cpu2.dtb.inst_misses 0 # ITB inst misses
+system.cpu2.dtb.read_hits 77077341 # DTB read hits
+system.cpu2.dtb.read_misses 441139 # DTB read misses
+system.cpu2.dtb.write_hits 58693711 # DTB write hits
+system.cpu2.dtb.write_misses 191612 # DTB write misses
+system.cpu2.dtb.flush_tlb 1283 # Number of times complete TLB was flushed
+system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu2.dtb.flush_tlb_mva_asid 14423 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_asid 383 # Number of times TLB was flushed by ASID
+system.cpu2.dtb.flush_entries 37244 # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults 88 # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults 5986 # Number of TLB faults due to prefetch
+system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu2.dtb.perms_faults 37589 # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses 77518480 # DTB read accesses
+system.cpu2.dtb.write_accesses 58885323 # DTB write accesses
+system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu2.dtb.hits 135771052 # DTB hits
+system.cpu2.dtb.misses 632751 # DTB misses
+system.cpu2.dtb.accesses 136403803 # DTB accesses
+system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu2.itb.inst_hits 69012170 # ITB inst hits
+system.cpu2.itb.inst_misses 76652 # ITB inst misses
+system.cpu2.itb.read_hits 0 # DTB read hits
+system.cpu2.itb.read_misses 0 # DTB read misses
+system.cpu2.itb.write_hits 0 # DTB write hits
+system.cpu2.itb.write_misses 0 # DTB write misses
+system.cpu2.itb.flush_tlb 1283 # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu2.itb.flush_tlb_mva_asid 14423 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_asid 383 # Number of times TLB was flushed by ASID
+system.cpu2.itb.flush_entries 28880 # Number of entries that have been flushed from TLB
+system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu2.itb.perms_faults 143189 # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.read_accesses 0 # DTB read accesses
+system.cpu2.itb.write_accesses 0 # DTB write accesses
+system.cpu2.itb.inst_accesses 69088822 # ITB inst accesses
+system.cpu2.itb.hits 69012170 # DTB hits
+system.cpu2.itb.misses 76652 # DTB misses
+system.cpu2.itb.accesses 69088822 # DTB accesses
+system.cpu2.numCycles 465978411 # number of cpu cycles simulated
+system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu2.fetch.icacheStallCycles 177853142 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 424737263 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 95476448 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 58618427 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 260785808 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 9691059 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 1879827 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles 8981 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 2007 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 3759830 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 120446 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 3389 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 68846411 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 2635973 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 29904 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 449258797 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.104850 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.350365 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 344689329 76.72% 76.72% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 13175573 2.93% 79.66% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 13441142 2.99% 82.65% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 9727641 2.17% 84.81% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 19687409 4.38% 89.20% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 6520571 1.45% 90.65% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 7057131 1.57% 92.22% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 6252659 1.39% 93.61% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 28707342 6.39% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::total 449258797 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.204895 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.911496 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 145040906 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 213951941 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 77038080 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 9368936 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 3856816 # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved 14196524 # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred 1002861 # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts 463271274 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 3090116 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 3856816 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 150407499 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 19371841 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 168106415 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 80889236 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 26624521 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 452059055 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 70033 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 1786376 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents 1304038 # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents 13315771 # Number of times rename has blocked due to SQ full
+system.cpu2.rename.FullRegisterEvents 3626 # Number of times there has been no free registers
+system.cpu2.rename.RenamedOperands 431846627 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 688168989 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 533483946 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 696961 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 360553438 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 71293189 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 9871202 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 8455912 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 51921554 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 73490892 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 61773042 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 9381483 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 10099562 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 429589038 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 9855415 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 428971223 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 602179 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 55645947 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 38557670 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 233014 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 449258797 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 0.954842 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.673453 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 283324312 63.06% 63.06% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 67630078 15.05% 78.12% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 31491211 7.01% 85.13% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 22481401 5.00% 90.13% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 17057859 3.80% 93.93% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 11702074 2.60% 96.53% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 7876083 1.75% 98.29% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 4650016 1.04% 99.32% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 3045763 0.68% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 449258797 # Number of insts issued each cycle
+system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 2154851 25.07% 25.07% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 17173 0.20% 25.27% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 1684 0.02% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 3571205 41.55% 66.84% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 2850152 33.16% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 289729991 67.54% 67.54% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 1034875 0.24% 67.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 48976 0.01% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 286 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 48552 0.01% 67.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 78627004 18.33% 86.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 59481539 13.87% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::total 428971223 # Type of FU issued
+system.cpu2.iq.rate 0.920582 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 8595065 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.020036 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 1315569237 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 495173501 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 412035990 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 829250 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 394091 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 358547 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 437122606 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 443682 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 3384290 # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu2.iew.lsq.thread0.squashedLoads 12185839 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 16415 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 485486 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 6512236 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu2.iew.lsq.thread0.rescheduledLoads 2660066 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 6807125 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu2.iew.iewSquashCycles 3856816 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 10978406 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 6986714 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 439540206 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 1332617 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 73490892 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 61773042 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 8263038 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 174452 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 6729882 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 485486 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 1971342 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 1708494 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 3679836 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 423953682 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 77064700 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 4393197 # Number of squashed instructions skipped in execute
+system.cpu2.iew.exec_swp 0 # number of swp insts executed
+system.cpu2.iew.exec_nop 95753 # number of nop insts executed
+system.cpu2.iew.exec_refs 135758319 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 78468818 # Number of branches executed
+system.cpu2.iew.exec_stores 58693619 # Number of stores executed
+system.cpu2.iew.exec_rate 0.909814 # Inst execution rate
+system.cpu2.iew.wb_sent 413267935 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 412394537 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 203830371 # num instructions producing a value
+system.cpu2.iew.wb_consumers 353623803 # num instructions consuming a value
+system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu2.iew.wb_rate 0.885008 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.576405 # average fanout of values written-back
+system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu2.commit.commitSquashedInsts 59831265 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 9622401 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 3310537 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 439132239 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 0.864557 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.865641 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 302394835 68.86% 68.86% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 65341940 14.88% 83.74% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 24189817 5.51% 89.25% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 10943430 2.49% 91.74% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 7703754 1.75% 93.50% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 4855013 1.11% 94.60% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 4328620 0.99% 95.59% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 2957558 0.67% 96.26% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 16417272 3.74% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::total 439132239 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 323541810 # Number of instructions committed
+system.cpu2.commit.committedOps 379654747 # Number of ops (including micro ops) committed
+system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu2.commit.refs 116565859 # Number of memory references committed
+system.cpu2.commit.loads 61305053 # Number of loads committed
+system.cpu2.commit.membars 2541238 # Number of memory barriers committed
+system.cpu2.commit.branches 72175443 # Number of branches committed
+system.cpu2.commit.fp_insts 344817 # Number of committed floating point instructions.
+system.cpu2.commit.int_insts 348881889 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 9429592 # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 262221519 69.07% 69.07% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 789172 0.21% 69.28% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv 36211 0.01% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 69.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc 41986 0.01% 69.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 69.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 61305053 16.15% 85.44% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 55260806 14.56% 100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::total 379654747 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 16417272 # number cycles where commit BW limit reached
+system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu2.rob.rob_reads 859553355 # The number of ROB reads
+system.cpu2.rob.rob_writes 889110894 # The number of ROB writes
+system.cpu2.timesIdled 2948522 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 16719614 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 99518769709 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 323541810 # Number of Instructions Simulated
+system.cpu2.committedOps 379654747 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 1.440242 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.440242 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.694328 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.694328 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 498743361 # number of integer regfile reads
+system.cpu2.int_regfile_writes 295064264 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 684469 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 420852 # number of floating regfile writes
+system.cpu2.cc_regfile_reads 90009576 # number of cc regfile reads
+system.cpu2.cc_regfile_writes 90769749 # number of cc regfile writes
+system.cpu2.misc_regfile_reads 1656723881 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 9715045 # number of misc regfile writes
+system.iocache.tags.replacements 115464 # number of replacements
+system.iocache.tags.tagsinuse 10.421560 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115480 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 13085874574509 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.547265 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.874295 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.221704 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.429643 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.651348 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 1040224 # Number of tag accesses
+system.iocache.tags.data_accesses 1040224 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8819 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8856 # number of ReadReq misses
+system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
+system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 65 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 65 # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8819 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8859 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
+system.iocache.overall_misses::realview.ide 8819 # number of overall misses
+system.iocache.overall_misses::total 8859 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet 2752000 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 1272471430 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 1275223430 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet 2752000 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide 1272471430 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 1275223430 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet 2752000 # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide 1272471430 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 1275223430 # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8819 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8856 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 106729 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 106729 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8819 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8859 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8819 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8859 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000609 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 0.000609 # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 74378.378378 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 144287.496315 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 143995.418925 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 68800 # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 144287.496315 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 143946.656508 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 68800 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 144287.496315 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 143946.656508 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 36080 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 3735 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 9.659973 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 106664 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.ReadReq_mshr_misses::realview.ethernet 16 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide 5668 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 5684 # number of ReadReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ethernet 16 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 5668 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 5684 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ethernet 16 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide 5668 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 5684 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 1920000 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 977655446 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 979575446 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2261356027 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2261356027 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet 1920000 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 977655446 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 979575446 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet 1920000 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 977655446 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 979575446 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 0.432432 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.642703 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 0.641825 # mshr miss rate for ReadReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 0.642703 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 0.641607 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 0.642703 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 0.641607 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 120000 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 172486.846507 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 172339.100281 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 120000 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 172486.846507 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 172339.100281 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 120000 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 172486.846507 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 172339.100281 # average overall mshr miss latency
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu2.kern.inst.arm 0 # number of arm instructions executed
+system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
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+atags_addr=134217728
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+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
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+early_kernel_symbols=false
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+kernel_addr_check=true
+load_addr_mask=268435455
+load_offset=2147483648
+machine_type=VExpress_EMM64
+mem_mode=timing
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+memories=system.realview.vram system.physmem system.realview.nvmem
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+phys_addr_range_64=40
+readfile=/work/gem5.latest/tests/halt.sh
+reset_addr_64=0
+symbolfile=
+work_begin_ckpt_count=0
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+work_begin_exit_count=0
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+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.bridge]
+type=Bridge
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+delay=50000
+eventq_index=0
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
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+
+[system.cf0]
+type=IdeDisk
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+delay=1000000
+driveID=master
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+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
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+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+eventq_index=0
+image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu0]
+type=DerivO3CPU
+children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+branchPred=system.cpu0.branchPred
+cachePorts=200
+checker=Null
+clk_domain=system.cpu_clk_domain
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
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+decodeToRenameDelay=1
+decodeWidth=8
+dispatchWidth=8
+do_checkpoint_insts=true
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+dstage2_mmu=system.cpu0.dstage2_mmu
+dtb=system.cpu0.dtb
+eventq_index=0
+fetchBufferSize=64
+fetchQueueSize=32
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu0.fuPool
+function_trace=false
+function_trace_start=0
+iewToCommitDelay=1
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+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+issueToExecuteDelay=1
+issueWidth=8
+istage2_mmu=system.cpu0.istage2_mmu
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+needsTSO=false
+numIQEntries=64
+numPhysCCRegs=1280
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+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
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+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+simpoint_start_insts=
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
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+smtROBThreshold=100
+socket_id=0
+squashWidth=8
+store_set_clear_period=250000
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+trapLatency=13
+wbWidth=8
+workload=
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+eventq_index=0
+globalCtrBits=2
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
+[system.cpu0.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
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+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
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+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu0.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+tlb=system.cpu0.dtb
+
+[system.cpu0.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
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+is_stage2=true
+size=32
+walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu0.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[5]
+
+[system.cpu0.dtb]
+type=ArmTLB
+children=walker
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+is_stage2=false
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[3]
+
+[system.cpu0.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
+eventq_index=0
+
+[system.cpu0.fuPool.FUList0]
+type=FUDesc
+children=opList
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+
+[system.cpu0.fuPool.FUList0.opList]
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+
+[system.cpu0.fuPool.FUList1]
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+eventq_index=0
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+
+[system.cpu0.fuPool.FUList1.opList0]
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+
+[system.cpu0.fuPool.FUList1.opList1]
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+
+[system.cpu0.fuPool.FUList2]
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+
+[system.cpu0.fuPool.FUList2.opList0]
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+
+[system.cpu0.fuPool.FUList2.opList1]
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+
+[system.cpu0.fuPool.FUList2.opList2]
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+
+[system.cpu0.fuPool.FUList3]
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+
+[system.cpu0.fuPool.FUList3.opList0]
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+
+[system.cpu0.fuPool.FUList3.opList1]
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+
+[system.cpu0.fuPool.FUList3.opList2]
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+
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+
+[system.cpu0.fuPool.FUList4.opList]
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+
+[system.cpu0.fuPool.FUList5]
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+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+eventq_index=0
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+
+[system.cpu0.fuPool.FUList5.opList00]
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
+[system.cpu0.fuPool.FUList5.opList16]
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+
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+
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+
+[system.cpu0.fuPool.FUList6]
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+
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+
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+
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+
+[system.cpu0.istage2_mmu]
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+
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+
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+
+[system.cpu1]
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+branchPred=system.cpu1.branchPred
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+fuPool=system.cpu1.fuPool
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+workload=
+
+[system.cpu1.branchPred]
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+
+[system.cpu1.fuPool]
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+
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+[system.cpu1.fuPool.FUList5.opList18]
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+[system.cpu1.fuPool.FUList5.opList19]
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+[system.cpu1.fuPool.FUList6]
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+
+[system.cpu1.fuPool.FUList6.opList]
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+[system.cpu1.fuPool.FUList7]
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+
+[system.cpu1.fuPool.FUList7.opList0]
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+[system.cpu1.fuPool.FUList7.opList1]
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+[system.cpu1.fuPool.FUList8]
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+
+[system.cpu1.fuPool.FUList8.opList]
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+
+[system.cpu1.isa]
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+fpsid=1090793632
+id_aa64afr0_el1=0
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+id_aa64dfr0_el1=1052678
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+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu1.istage2_mmu]
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+
+[system.cpu1.istage2_mmu.stage2_tlb]
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+
+[system.cpu1.istage2_mmu.stage2_tlb.walker]
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+
+[system.cpu1.itb]
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+
+[system.cpu1.itb.walker]
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+
+[system.cpu1.tracer]
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+
+[system.cpu_clk_domain]
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+clock=500
+domain_id=-1
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+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
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+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
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+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+use_default_range=true
+width=8
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
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+assoc=8
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+size=1024
+system=system
+tags=system.iocache.tags
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+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
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+
+[system.l2c]
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+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.l2c.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=2147483648:2415919103
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
+tWTR=7500
+tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 19:59:19
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3 -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+ 0: system.cpu0.isa: ISA system set to: 0x42b8b00 0x42b8b00
+ 0: system.cpu1.isa: ISA system set to: 0x42b8b00 0x42b8b00
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 51.316753 # Number of seconds simulated
+sim_ticks 51316753294500 # Number of ticks simulated
+final_tick 51316753294500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 136598 # Simulator instruction rate (inst/s)
+host_op_rate 160520 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 7792719388 # Simulator tick rate (ticks/s)
+host_mem_usage 670460 # Number of bytes of host memory used
+host_seconds 6585.22 # Real time elapsed on the host
+sim_insts 899526584 # Number of instructions simulated
+sim_ops 1057057755 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::realview.ide 436032 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 324288 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 511488 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 3575488 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 35714136 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 305664 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 479488 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 3431104 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 34340592 # Number of bytes read from this memory
+system.physmem.bytes_read::total 79118280 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 3575488 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 3431104 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 7006592 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 46041344 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 50417380 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 49769472 # Number of bytes written to this memory
+system.physmem.bytes_written::total 153054692 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 6813 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 5067 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 7992 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 55867 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 558041 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 4776 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 7492 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 53611 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 536577 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1236236 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 719396 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 790023 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 777648 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 2393731 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 8497 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 6319 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 9967 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 69675 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 695955 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 5956 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 9344 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 66861 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 669189 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1541763 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 69675 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 66861 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 136536 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 897199 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 133027 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 982474 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 969848 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2982548 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 897199 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 141524 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 6319 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 9967 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 69675 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1678429 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 5956 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 9344 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 66861 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 1639037 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4524311 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1236236 # Number of read requests accepted
+system.physmem.writeReqs 2393731 # Number of write requests accepted
+system.physmem.readBursts 1236236 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 2393731 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 78915968 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 203136 # Total number of bytes read from write queue
+system.physmem.bytesWritten 148972800 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 79118280 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 153054692 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 3174 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 66016 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 38473 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 78969 # Per bank write bursts
+system.physmem.perBankRdBursts::1 76054 # Per bank write bursts
+system.physmem.perBankRdBursts::2 70113 # Per bank write bursts
+system.physmem.perBankRdBursts::3 71416 # Per bank write bursts
+system.physmem.perBankRdBursts::4 73251 # Per bank write bursts
+system.physmem.perBankRdBursts::5 79391 # Per bank write bursts
+system.physmem.perBankRdBursts::6 70957 # Per bank write bursts
+system.physmem.perBankRdBursts::7 70585 # Per bank write bursts
+system.physmem.perBankRdBursts::8 72320 # Per bank write bursts
+system.physmem.perBankRdBursts::9 103108 # Per bank write bursts
+system.physmem.perBankRdBursts::10 75527 # Per bank write bursts
+system.physmem.perBankRdBursts::11 73923 # Per bank write bursts
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+system.physmem.perBankRdBursts::13 84199 # Per bank write bursts
+system.physmem.perBankRdBursts::14 79405 # Per bank write bursts
+system.physmem.perBankRdBursts::15 79777 # Per bank write bursts
+system.physmem.perBankWrBursts::0 143281 # Per bank write bursts
+system.physmem.perBankWrBursts::1 127790 # Per bank write bursts
+system.physmem.perBankWrBursts::2 148899 # Per bank write bursts
+system.physmem.perBankWrBursts::3 137605 # Per bank write bursts
+system.physmem.perBankWrBursts::4 197374 # Per bank write bursts
+system.physmem.perBankWrBursts::5 124383 # Per bank write bursts
+system.physmem.perBankWrBursts::6 109194 # Per bank write bursts
+system.physmem.perBankWrBursts::7 129383 # Per bank write bursts
+system.physmem.perBankWrBursts::8 151210 # Per bank write bursts
+system.physmem.perBankWrBursts::9 186118 # Per bank write bursts
+system.physmem.perBankWrBursts::10 208778 # Per bank write bursts
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+system.physmem.perBankWrBursts::12 123729 # Per bank write bursts
+system.physmem.perBankWrBursts::13 141617 # Per bank write bursts
+system.physmem.perBankWrBursts::14 124170 # Per bank write bursts
+system.physmem.perBankWrBursts::15 132827 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 128 # Number of times write queue was full causing retry
+system.physmem.totGap 51316752176000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 13 # Read request sizes (log2)
+system.physmem.readPktSize::4 2 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 1236221 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 1 # Write request sizes (log2)
+system.physmem.writePktSize::3 2572 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 2391158 # Write request sizes (log2)
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+system.physmem.bytesPerActivate::samples 678102 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 336.067624 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 184.620268 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 366.767956 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 271362 40.02% 40.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 148250 21.86% 61.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 55753 8.22% 70.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 26626 3.93% 74.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 20429 3.01% 77.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 13236 1.95% 78.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 10909 1.61% 80.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 14852 2.19% 82.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 116685 17.21% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 678102 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 81261 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 15.173946 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 173.903253 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 81255 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095 3 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-12287 2 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 81261 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 81261 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 28.644737 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 24.485973 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 20.407420 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-7 56 0.07% 0.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-15 139 0.17% 0.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23 47231 58.12% 58.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31 7834 9.64% 68.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39 13023 16.03% 84.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47 3682 4.53% 88.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55 2148 2.64% 91.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63 950 1.17% 92.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71 2747 3.38% 95.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79 1058 1.30% 97.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87 767 0.94% 98.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95 240 0.30% 98.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103 341 0.42% 98.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111 185 0.23% 98.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119 486 0.60% 99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127 8 0.01% 99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135 31 0.04% 99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143 23 0.03% 99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151 18 0.02% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159 31 0.04% 99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167 73 0.09% 99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175 62 0.08% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183 51 0.06% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191 8 0.01% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199 17 0.02% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207 1 0.00% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215 17 0.02% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223 5 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239 1 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247 9 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255 7 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271 6 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-279 2 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 81261 # Writes before turning the bus around for reads
+system.physmem.totQLat 27538646010 # Total ticks spent queuing
+system.physmem.totMemAccLat 50658558510 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 6165310000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 22333.55 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 41083.55 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.54 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.90 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.54 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 10.42 # Average write queue length when enqueuing
+system.physmem.readRowHits 964323 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1918333 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 78.21 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 82.41 # Row buffer hit rate for writes
+system.physmem.avgGap 14136974.85 # Average gap between requests
+system.physmem.pageHitRate 80.96 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 49243370940756 # Time in different power states
+system.physmem.memoryStateTime::REF 1713579140000 # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem.memoryStateTime::ACT 359802419244 # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem.actEnergy::0 2507478120 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 2618973000 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 1368167625 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 1429003125 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 4607662800 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 5010142800 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 7244050320 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 7839445680 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 3351760797840 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 3351760797840 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 1283842483380 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 1294175764575 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 29663873874750 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 29654809593000 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 34315204514835 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 34317643720020 # Total energy per rank (pJ)
+system.physmem.averagePower::0 668.694001 # Core power per rank (mW)
+system.physmem.averagePower::1 668.741533 # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 1408 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 2212 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 768 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 1408 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 2176 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 12 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 22 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 27 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 43 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 27 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 42 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10027.818041 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.023282 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10029.869565 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75638.343667 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 76875.600564 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 76246.636268 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66653.140320 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 64872.745996 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64880.809955 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73632.337498 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65007.845268 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 65290.240657 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65332.835824 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74260.183414 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 73112.083134 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66653.140320 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 64872.745996 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64880.809955 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73632.337498 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65007.845268 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 65290.240657 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65332.835824 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74260.183414 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 73112.083134 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq 25440595 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 25432319 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 33859 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 33859 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 7101304 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 1671768 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 1565098 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 50543 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 14 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 50557 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 2138912 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 2138912 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 32275606 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29216023 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 915477 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2586660 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 64993766 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1032811840 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1154800272 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3083944 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8731728 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 2199427784 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 664547 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 36349119 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 5.003178 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.056284 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 36233600 99.68% 99.68% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 115519 0.32% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 36349119 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 52855909091 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 2566500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 72684313037 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 43208232692 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 533902381 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 1509803178 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 40375 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40375 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136543 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136733 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 190 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230946 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230946 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 354216 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334216 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334216 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7492622 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 981411596 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 178989221 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.cpu0.branchPred.lookups 132719565 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 89993236 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 5932836 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 90710148 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 64716268 # Number of BTB hits
+system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu0.branchPred.BTBHitPct 71.344022 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 17452568 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 191045 # Number of incorrect RAS predictions.
+system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 106360367 # DTB read hits
+system.cpu0.dtb.read_misses 615971 # DTB read misses
+system.cpu0.dtb.write_hits 81393112 # DTB write hits
+system.cpu0.dtb.write_misses 266071 # DTB write misses
+system.cpu0.dtb.flush_tlb 1087 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 22107 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 543 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 56260 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 229 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 9041 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 57266 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 106976338 # DTB read accesses
+system.cpu0.dtb.write_accesses 81659183 # DTB write accesses
+system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dtb.hits 187753479 # DTB hits
+system.cpu0.dtb.misses 882042 # DTB misses
+system.cpu0.dtb.accesses 188635521 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.inst_hits 95391690 # ITB inst hits
+system.cpu0.itb.inst_misses 104013 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.flush_tlb 1087 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 22107 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 543 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 41837 # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults 207435 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.inst_accesses 95495703 # ITB inst accesses
+system.cpu0.itb.hits 95391690 # DTB hits
+system.cpu0.itb.misses 104013 # DTB misses
+system.cpu0.itb.accesses 95495703 # DTB accesses
+system.cpu0.numCycles 684418323 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.fetch.icacheStallCycles 248384937 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 589536301 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 132719565 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 82168836 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 395321090 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 13514905 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 2556917 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 20977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles 5408 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles 5551519 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 175554 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 1648 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 95166614 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 3687085 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 41415 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 658775231 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.047637 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.297009 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 512971129 77.87% 77.87% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 18432133 2.80% 80.67% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 18348661 2.79% 83.45% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 13411814 2.04% 85.49% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 28741584 4.36% 89.85% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 9038627 1.37% 91.22% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 9794305 1.49% 92.71% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 8428424 1.28% 93.99% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 39608554 6.01% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::total 658775231 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.193916 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.861368 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 200994103 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 333361407 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 105045785 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 14028144 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 5343793 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 19697248 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 1433030 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 641923192 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 4435962 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 5343793 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 208785389 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 28964603 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 262496699 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 111103202 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 42079210 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 626316852 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 80050 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 2362679 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 1879089 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 21911490 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents 5199 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 599577423 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 966250594 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 740756106 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 877957 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 502593400 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 96984018 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 15462984 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 13497488 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 79320336 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 100980804 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 85727659 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 13927717 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 14882282 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 593862929 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 15564372 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 595387827 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 831090 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 76362787 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 53001437 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 356285 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 658775231 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.903780 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.628017 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 423143545 64.23% 64.23% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 100533840 15.26% 79.49% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 43588427 6.62% 86.11% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 31078402 4.72% 90.83% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 23328962 3.54% 94.37% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 15913876 2.42% 96.78% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 10814135 1.64% 98.43% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 6320463 0.96% 99.38% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 4053581 0.62% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 658775231 # Number of insts issued each cycle
+system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 2985575 25.28% 25.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 23079 0.20% 25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 3324 0.03% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 2 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 5019003 42.51% 68.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 3776946 31.99% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 402885613 67.67% 67.67% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 1422777 0.24% 67.91% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 64552 0.01% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 67 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 58868 0.01% 67.93% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.93% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.93% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.93% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 108485553 18.22% 86.15% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 82470396 13.85% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::total 595387827 # Type of FU issued
+system.cpu0.iq.rate 0.869918 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 11807929 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.019832 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 1861125914 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 685987174 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 571772727 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 1063990 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 505463 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 456200 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 606627126 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 568629 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 4761213 # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu0.iew.lsq.thread0.squashedLoads 16799552 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 22497 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 714171 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 9156054 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu0.iew.lsq.thread0.rescheduledLoads 3900719 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 9933744 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu0.iew.iewSquashCycles 5343793 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 15674856 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 11567544 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 609566615 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 1794840 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 100980804 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 85727659 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 13194913 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 258499 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 11189475 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 714171 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 2685620 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 2322794 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 5008414 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 588648436 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 106351748 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 5872018 # Number of squashed instructions skipped in execute
+system.cpu0.iew.exec_swp 0 # number of swp insts executed
+system.cpu0.iew.exec_nop 139314 # number of nop insts executed
+system.cpu0.iew.exec_refs 187749395 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 108957932 # Number of branches executed
+system.cpu0.iew.exec_stores 81397647 # Number of stores executed
+system.cpu0.iew.exec_rate 0.860071 # Inst execution rate
+system.cpu0.iew.wb_sent 573457881 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 572228927 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 281462520 # num instructions producing a value
+system.cpu0.iew.wb_consumers 488752044 # num instructions consuming a value
+system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu0.iew.wb_rate 0.836081 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.575880 # average fanout of values written-back
+system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu0.commit.commitSquashedInsts 82137816 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 15208087 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 4518905 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 644781794 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.817863 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.810443 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 449449526 69.71% 69.71% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 97358122 15.10% 84.81% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 33578375 5.21% 90.01% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 14917712 2.31% 92.33% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 10631887 1.65% 93.98% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 6530680 1.01% 94.99% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 5822825 0.90% 95.89% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 3984235 0.62% 96.51% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 22508432 3.49% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::total 644781794 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 448706085 # Number of instructions committed
+system.cpu0.commit.committedOps 527343007 # Number of ops (including micro ops) committed
+system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu0.commit.refs 160752856 # Number of memory references committed
+system.cpu0.commit.loads 84181251 # Number of loads committed
+system.cpu0.commit.membars 3744837 # Number of memory barriers committed
+system.cpu0.commit.branches 100346754 # Number of branches committed
+system.cpu0.commit.fp_insts 436641 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 484032213 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 13338237 # Number of function calls committed.
+system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 365400890 69.29% 69.29% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 1092025 0.21% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv 47793 0.01% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc 49443 0.01% 69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 84181251 15.96% 85.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 76571605 14.52% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::total 527343007 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 22508432 # number cycles where commit BW limit reached
+system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu0.rob.rob_reads 1227661689 # The number of ROB reads
+system.cpu0.rob.rob_writes 1232973286 # The number of ROB writes
+system.cpu0.timesIdled 4104064 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 25643092 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 54070741689 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 448706085 # Number of Instructions Simulated
+system.cpu0.committedOps 527343007 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 1.525315 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 1.525315 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.655602 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.655602 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 693970255 # number of integer regfile reads
+system.cpu0.int_regfile_writes 408353798 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 822679 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 492268 # number of floating regfile writes
+system.cpu0.cc_regfile_reads 125884227 # number of cc regfile reads
+system.cpu0.cc_regfile_writes 126919674 # number of cc regfile writes
+system.cpu0.misc_regfile_reads 2342378074 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 15341166 # number of misc regfile writes
+system.cpu0.icache.tags.replacements 16116656 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.960235 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 173052626 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 16117168 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 10.737161 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 11668105000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 286.930366 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 225.029869 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.560411 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst 0.439511 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.999922 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses 206428941 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 206428941 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 86457913 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 86594713 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 173052626 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 86457913 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst 86594713 # number of demand (read+write) hits
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+system.cpu0.icache.overall_hits::total 173052626 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 8696178 # number of ReadReq misses
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+system.cpu0.icache.ReadReq_misses::total 17259032 # number of ReadReq misses
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+system.cpu0.icache.overall_misses::total 17259032 # number of overall misses
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+system.cpu0.icache.overall_miss_latency::total 229504475101 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 95154091 # number of ReadReq accesses(hits+misses)
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+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089986 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.090688 # miss rate for ReadReq accesses
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+system.cpu0.icache.overall_miss_rate::total 0.090688 # miss rate for overall accesses
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+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13311.573191 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13297.644683 # average ReadReq miss latency
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+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13311.573191 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13297.644683 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13283.929717 # average overall miss latency
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+system.cpu0.icache.overall_avg_miss_latency::total 13297.644683 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 66644 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 6194 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 10.759445 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 579009 # number of ReadReq MSHR hits
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+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 93158518069 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 187537231993 # number of demand (read+write) MSHR miss cycles
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+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 93158518069 # number of overall MSHR miss cycles
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+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1511876000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 916338250 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 595537750 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total 1511876000 # number of overall MSHR uncacheable cycles
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+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.084072 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084689 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.084072 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.084689 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.084072 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.084689 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11627.048042 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11644.648822 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11635.784517 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11627.048042 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11644.648822 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11635.784517 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11627.048042 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11644.648822 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11635.784517 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.dcache.tags.replacements 10609337 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.983537 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 304225194 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 10609849 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 28.673848 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 1654841000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 299.046294 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data 212.937243 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.584075 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data 0.415893 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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+system.cpu0.dcache.demand_mshr_miss_rate::total 0.024476 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028855 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027884 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.028368 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15462.887815 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15452.055657 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15457.526908 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40555.548912 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41159.303892 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40851.286367 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20112.349754 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19285.529383 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19705.808199 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12808.304888 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13049.155402 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12927.818140 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15277.444444 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18699.400000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16499.571429 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22449.342881 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22505.203842 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22476.910456 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22117.008154 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22050.184269 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22084.047493 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.branchPred.lookups 132695624 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 90331188 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 5850625 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 91191115 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 65101533 # Number of BTB hits
+system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu1.branchPred.BTBHitPct 71.390215 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 17167330 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 185817 # Number of incorrect RAS predictions.
+system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.inst_hits 0 # ITB inst hits
+system.cpu1.dtb.inst_misses 0 # ITB inst misses
+system.cpu1.dtb.read_hits 106438912 # DTB read hits
+system.cpu1.dtb.read_misses 617019 # DTB read misses
+system.cpu1.dtb.write_hits 81859907 # DTB write hits
+system.cpu1.dtb.write_misses 262953 # DTB write misses
+system.cpu1.dtb.flush_tlb 1095 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 21187 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 524 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 54609 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 175 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 8788 # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults 55422 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 107055931 # DTB read accesses
+system.cpu1.dtb.write_accesses 82122860 # DTB write accesses
+system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dtb.hits 188298819 # DTB hits
+system.cpu1.dtb.misses 879972 # DTB misses
+system.cpu1.dtb.accesses 189178791 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.inst_hits 95390425 # ITB inst hits
+system.cpu1.itb.inst_misses 103002 # ITB inst misses
+system.cpu1.itb.read_hits 0 # DTB read hits
+system.cpu1.itb.read_misses 0 # DTB read misses
+system.cpu1.itb.write_hits 0 # DTB write hits
+system.cpu1.itb.write_misses 0 # DTB write misses
+system.cpu1.itb.flush_tlb 1095 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 21187 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 524 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 40480 # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults 202732 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses 0 # DTB read accesses
+system.cpu1.itb.write_accesses 0 # DTB write accesses
+system.cpu1.itb.inst_accesses 95493427 # ITB inst accesses
+system.cpu1.itb.hits 95390425 # DTB hits
+system.cpu1.itb.misses 103002 # DTB misses
+system.cpu1.itb.accesses 95493427 # DTB accesses
+system.cpu1.numCycles 672741965 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.fetch.icacheStallCycles 246640136 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 590780429 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 132695624 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 82268863 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 386429410 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 13305333 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 2543340 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 19984 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles 4103 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles 5378147 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 163710 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 1900 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 95165721 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 3597908 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 39974 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 647833125 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.067316 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.314702 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 501796172 77.46% 77.46% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 18436133 2.85% 80.30% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 18485753 2.85% 83.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 13501389 2.08% 85.24% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 28566375 4.41% 89.65% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 9032490 1.39% 91.04% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 9749840 1.50% 92.55% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 8516033 1.31% 93.86% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 39748940 6.14% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::total 647833125 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.197246 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.878168 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 200194473 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 322668892 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 105843727 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 13827399 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 5296426 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 19681907 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 1375410 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 644487824 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 4238266 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 5296426 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 207887374 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 28633275 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 252987067 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 111782593 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 41244065 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 628972841 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 101309 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 2336709 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 1765264 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 21471594 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents 4932 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 601986706 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 968135800 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 743741537 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 921788 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 504541868 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 97444838 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 15091316 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 13114684 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 77880403 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 101483347 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 86159667 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 13596196 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 14436334 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 596800589 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 15137564 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 597335702 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 820098 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 76624490 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 53348640 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 353802 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 647833125 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.922052 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.644482 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 412924221 63.74% 63.74% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 99304245 15.33% 79.07% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 43461350 6.71% 85.78% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 31157407 4.81% 90.59% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 23474401 3.62% 94.21% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 16043027 2.48% 96.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 10934122 1.69% 98.37% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 6355751 0.98% 99.35% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 4178601 0.65% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 647833125 # Number of insts issued each cycle
+system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 3005947 25.29% 25.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 24266 0.20% 25.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 2049 0.02% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 4 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 4972015 41.83% 67.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 3881824 32.66% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu1.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 404183986 67.66% 67.66% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 1499549 0.25% 67.92% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 69544 0.01% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 173 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 16 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 70359 0.01% 67.94% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.94% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.94% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.94% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 108574781 18.18% 86.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 82937260 13.88% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::total 597335702 # Type of FU issued
+system.cpu1.iq.rate 0.887912 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 11886105 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.019899 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 1854102856 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 688730877 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 574087973 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 1107876 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 525044 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 478100 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 608629489 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 592317 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 4742542 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu1.iew.lsq.thread0.squashedLoads 16809176 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 22821 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 704571 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 9065130 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu1.iew.lsq.thread0.rescheduledLoads 3904838 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 9464363 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu1.iew.iewSquashCycles 5296426 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 15503911 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 11248845 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 612073318 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 1785807 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 101483347 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 86159667 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 12828539 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 251466 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 10878256 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 704571 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 2684400 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 2302903 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 4987303 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 590552056 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 106426998 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 5916414 # Number of squashed instructions skipped in execute
+system.cpu1.iew.exec_swp 0 # number of swp insts executed
+system.cpu1.iew.exec_nop 135165 # number of nop insts executed
+system.cpu1.iew.exec_refs 188286771 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 109138667 # Number of branches executed
+system.cpu1.iew.exec_stores 81859773 # Number of stores executed
+system.cpu1.iew.exec_rate 0.877828 # Inst execution rate
+system.cpu1.iew.wb_sent 575751009 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 574566073 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 283200911 # num instructions producing a value
+system.cpu1.iew.wb_consumers 491579029 # num instructions consuming a value
+system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu1.iew.wb_rate 0.854066 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.576105 # average fanout of values written-back
+system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu1.commit.commitSquashedInsts 82275122 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 14783762 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 4494113 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 633863514 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.835692 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.830647 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 439265925 69.30% 69.30% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 95913161 15.13% 84.43% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 33589452 5.30% 89.73% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 15187737 2.40% 92.13% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 10634281 1.68% 93.80% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 6553980 1.03% 94.84% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 5971917 0.94% 95.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 4055542 0.64% 96.42% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 22691519 3.58% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::total 633863514 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 450820499 # Number of instructions committed
+system.cpu1.commit.committedOps 529714748 # Number of ops (including micro ops) committed
+system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu1.commit.refs 161768708 # Number of memory references committed
+system.cpu1.commit.loads 84674171 # Number of loads committed
+system.cpu1.commit.membars 3651509 # Number of memory barriers committed
+system.cpu1.commit.branches 100548022 # Number of branches committed
+system.cpu1.commit.fp_insts 459048 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 486295386 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 13182426 # Number of function calls committed.
+system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 366696799 69.23% 69.23% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 1136926 0.21% 69.44% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 51579 0.01% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 60694 0.01% 69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 84674171 15.98% 85.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 77094537 14.55% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::total 529714748 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 22691519 # number cycles where commit BW limit reached
+system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu1.rob.rob_reads 1219313535 # The number of ROB reads
+system.cpu1.rob.rob_writes 1237971918 # The number of ROB writes
+system.cpu1.timesIdled 4075861 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 24908840 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 47205322910 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 450820499 # Number of Instructions Simulated
+system.cpu1.committedOps 529714748 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 1.492261 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 1.492261 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.670124 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.670124 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 696110289 # number of integer regfile reads
+system.cpu1.int_regfile_writes 410149745 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 853704 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 525664 # number of floating regfile writes
+system.cpu1.cc_regfile_reads 126283635 # number of cc regfile reads
+system.cpu1.cc_regfile_writes 127381072 # number of cc regfile writes
+system.cpu1.misc_regfile_reads 2332819849 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 14911197 # number of misc regfile writes
+system.iocache.tags.replacements 115453 # number of replacements
+system.iocache.tags.tagsinuse 10.425607 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115469 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 13088656983000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.544416 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.881191 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.221526 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.430074 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.651600 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 1041134 # Number of tag accesses
+system.iocache.tags.data_accesses 1041134 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8809 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8846 # number of ReadReq misses
+system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
+system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 190 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 190 # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8809 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8849 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
+system.iocache.overall_misses::realview.ide 8809 # number of overall misses
+system.iocache.overall_misses::total 8849 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet 5533000 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 1914739091 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 1920272091 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet 5872000 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide 1914739091 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 1920611091 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet 5872000 # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide 1914739091 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 1920611091 # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8809 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8846 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 106854 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 106854 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8809 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8849 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8809 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8849 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.001778 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 0.001778 # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149540.540541 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 217361.685889 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 217078.011644 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 146800 # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 217361.685889 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 217042.726975 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 146800 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 217361.685889 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 217042.726975 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 52653 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 9.590710 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 106664 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide 8809 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 8846 # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 8809 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 8849 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide 8809 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 8849 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3609000 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 1456535121 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 1460144121 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6643047696 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6643047696 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet 3792000 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 1456535121 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 1460327121 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet 3792000 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 1456535121 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 1460327121 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97540.540541 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165346.250539 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 165062.640855 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 94800 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 165346.250539 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 165027.361397 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 94800 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 165346.250539 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 165027.361397 # average overall mshr miss latency
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 16389 # number of quiesce instructions executed
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
+atags_addr=134217728
+boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
+eventq_index=0
+flags_addr=469827632
+gic_cpu_addr=738205696
+have_generic_timer=false
+have_large_asid_64=false
+have_lpae=false
+have_security=false
+have_virtualization=false
+highest_el_is_64=false
+init_param=0
+kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel_addr_check=true
+load_addr_mask=268435455
+load_offset=2147483648
+machine_type=VExpress_EMM64
+mem_mode=timing
+mem_ranges=2147483648:2415919103
+memories=system.realview.nvmem system.physmem system.realview.vram
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+phys_addr_range_64=40
+readfile=/work/gem5.latest/tests/halt.sh
+reset_addr_64=0
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.bridge]
+type=Bridge
+clk_domain=system.clk_domain
+delay=50000
+eventq_index=0
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+eventq_index=0
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+eventq_index=0
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+eventq_index=0
+image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu0]
+type=TimingSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu0.dstage2_mmu
+dtb=system.cpu0.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+istage2_mmu=system.cpu0.istage2_mmu
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+workload=
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu0.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+tlb=system.cpu0.dtb
+
+[system.cpu0.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu0.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[5]
+
+[system.cpu0.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[3]
+
+[system.cpu0.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=1
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu0.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu0.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu0.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+tlb=system.cpu0.itb
+
+[system.cpu0.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu0.istage2_mmu.stage2_tlb.walker
+
+[system.cpu0.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[4]
+
+[system.cpu0.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu0.itb.walker
+
+[system.cpu0.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[2]
+
+[system.cpu0.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu1]
+type=TimingSimpleCPU
+children=dstage2_mmu dtb isa istage2_mmu itb tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu1.dstage2_mmu
+dtb=system.cpu1.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=Null
+isa=system.cpu1.isa
+istage2_mmu=system.cpu1.istage2_mmu
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=true
+system=system
+tracer=system.cpu1.tracer
+workload=
+
+[system.cpu1.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+tlb=system.cpu1.dtb
+
+[system.cpu1.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu1.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu1.dtb.walker
+
+[system.cpu1.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu1.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+tlb=system.cpu1.itb
+
+[system.cpu1.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu1.istage2_mmu.stage2_tlb.walker
+
+[system.cpu1.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+use_default_range=true
+width=8
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
+eventq_index=0
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.l2c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.l2c.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=2147483648:2415919103
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
+tWTR=7500
+tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
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--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 09:18:22
+gem5 started Oct 29 2014 13:24:01
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+ 0: system.cpu0.isa: ISA system set to: 0x5b6db00 0x5b6db00
+ 0: system.cpu1.isa: ISA system set to: 0x5b6db00 0x5b6db00
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 51.861029 # Number of seconds simulated
+sim_ticks 51861029093000 # Number of ticks simulated
+final_tick 51861029093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 655308 # Simulator instruction rate (inst/s)
+host_op_rate 770071 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 39176575505 # Simulator tick rate (ticks/s)
+host_mem_usage 667356 # Number of bytes of host memory used
+host_seconds 1323.78 # Real time elapsed on the host
+sim_insts 867480679 # Number of instructions simulated
+sim_ops 1019401547 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.ide 385536 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 227072 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 396672 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 2360360 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 30329136 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 251456 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 422720 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 2259596 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 29551000 # Number of bytes read from this memory
+system.physmem.bytes_read::total 66183548 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 2360360 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 2259596 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 4619956 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 36744512 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 49590532 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 50357856 # Number of bytes written to this memory
+system.physmem.bytes_written::total 143519396 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 6024 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 3548 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 6198 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 64295 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 473896 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 3929 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 6605 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 48299 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 461744 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1074538 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 574133 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 774853 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 789092 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 2244742 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 7434 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 4378 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 7649 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 45513 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 584816 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 4849 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 8151 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 43570 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 569811 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1276171 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 45513 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 43570 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 89083 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 708519 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 131631 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 956220 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 971015 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2767384 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 708519 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 139065 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 4378 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 7649 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 45513 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1541035 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 4849 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 8151 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 43570 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 1540827 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4043555 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1074538 # Number of read requests accepted
+system.physmem.writeReqs 2244742 # Number of write requests accepted
+system.physmem.readBursts 1074538 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 2244742 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 68582272 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 188160 # Total number of bytes read from write queue
+system.physmem.bytesWritten 138957696 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 66183548 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 143519396 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 2940 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 73507 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 34757 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 71255 # Per bank write bursts
+system.physmem.perBankRdBursts::1 63640 # Per bank write bursts
+system.physmem.perBankRdBursts::2 66612 # Per bank write bursts
+system.physmem.perBankRdBursts::3 61740 # Per bank write bursts
+system.physmem.perBankRdBursts::4 60545 # Per bank write bursts
+system.physmem.perBankRdBursts::5 71198 # Per bank write bursts
+system.physmem.perBankRdBursts::6 58053 # Per bank write bursts
+system.physmem.perBankRdBursts::7 57022 # Per bank write bursts
+system.physmem.perBankRdBursts::8 61158 # Per bank write bursts
+system.physmem.perBankRdBursts::9 112029 # Per bank write bursts
+system.physmem.perBankRdBursts::10 66876 # Per bank write bursts
+system.physmem.perBankRdBursts::11 66235 # Per bank write bursts
+system.physmem.perBankRdBursts::12 62785 # Per bank write bursts
+system.physmem.perBankRdBursts::13 68778 # Per bank write bursts
+system.physmem.perBankRdBursts::14 63805 # Per bank write bursts
+system.physmem.perBankRdBursts::15 59867 # Per bank write bursts
+system.physmem.perBankWrBursts::0 127784 # Per bank write bursts
+system.physmem.perBankWrBursts::1 113302 # Per bank write bursts
+system.physmem.perBankWrBursts::2 227736 # Per bank write bursts
+system.physmem.perBankWrBursts::3 110987 # Per bank write bursts
+system.physmem.perBankWrBursts::4 128170 # Per bank write bursts
+system.physmem.perBankWrBursts::5 133310 # Per bank write bursts
+system.physmem.perBankWrBursts::6 113658 # Per bank write bursts
+system.physmem.perBankWrBursts::7 104648 # Per bank write bursts
+system.physmem.perBankWrBursts::8 114567 # Per bank write bursts
+system.physmem.perBankWrBursts::9 129854 # Per bank write bursts
+system.physmem.perBankWrBursts::10 127393 # Per bank write bursts
+system.physmem.perBankWrBursts::11 118149 # Per bank write bursts
+system.physmem.perBankWrBursts::12 133562 # Per bank write bursts
+system.physmem.perBankWrBursts::13 181801 # Per bank write bursts
+system.physmem.perBankWrBursts::14 180172 # Per bank write bursts
+system.physmem.perBankWrBursts::15 126121 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 18 # Number of times write queue was full causing retry
+system.physmem.totGap 51861026536500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 43101 # Read request sizes (log2)
+system.physmem.readPktSize::3 13 # Read request sizes (log2)
+system.physmem.readPktSize::4 2 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 1031422 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 1 # Write request sizes (log2)
+system.physmem.writePktSize::3 2572 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 2242169 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1023941 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 42084 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 2127 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::4 705 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 1684 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::2 1640 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::12 1611 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::14 1607 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::34 2012 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::52 201 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::54 149 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 136 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 124 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 99 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 77 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 38 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 634955 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 326.856851 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 182.109909 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 357.606066 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 251774 39.65% 39.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 143572 22.61% 62.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 53819 8.48% 70.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 28426 4.48% 75.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 19160 3.02% 78.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 14370 2.26% 80.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 10671 1.68% 82.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 11114 1.75% 83.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 102049 16.07% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 634955 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 109417 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 9.793551 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 155.538286 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 109409 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095 2 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-6143 2 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-16383 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::18432-20479 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::43008-45055 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 109417 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 109417 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.843480 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 19.459226 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 5.174824 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3 51 0.05% 0.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7 17 0.02% 0.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11 14 0.01% 0.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15 145 0.13% 0.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 52162 47.67% 47.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 51235 46.83% 94.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 1984 1.81% 96.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 1760 1.61% 98.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 951 0.87% 99.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 159 0.15% 99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 147 0.13% 99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 71 0.06% 99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 99 0.09% 99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 20 0.02% 99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 21 0.02% 99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 18 0.02% 99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 372 0.34% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 33 0.03% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 39 0.04% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 25 0.02% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 36 0.03% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 1 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 9 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 4 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 2 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 1 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 4 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 9 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 4 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 13 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 7 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 109417 # Writes before turning the bus around for reads
+system.physmem.totQLat 11994975500 # Total ticks spent queuing
+system.physmem.totMemAccLat 32087438000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 5357990000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11193.54 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 29943.54 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.32 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.68 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.28 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 10.58 # Average write queue length when enqueuing
+system.physmem.readRowHits 810923 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1796931 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 75.67 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 82.76 # Row buffer hit rate for writes
+system.physmem.avgGap 15624179.50 # Average gap between requests
+system.physmem.pageHitRate 80.42 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 49513780638000 # Time in different power states
+system.physmem.memoryStateTime::REF 1731753660000 # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem.memoryStateTime::ACT 615493469500 # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem.actEnergy::0 2375299080 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 2424960720 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 1296046125 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 1323143250 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 3978491400 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 4379902800 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 6866175600 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 7203291120 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 3387310158960 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 3387310158960 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 1391264257590 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 1403130352860 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 29896208916750 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 29885800061250 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 34689299345505 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 34691571870960 # Total energy per rank (pJ)
+system.physmem.averagePower::0 668.889557 # Core power per rank (mW)
+system.physmem.averagePower::1 668.933377 # Core power per rank (mW)
+system.membus.trans_dist::ReadReq 477149 # Transaction distribution
+system.membus.trans_dist::ReadResp 477149 # Transaction distribution
+system.membus.trans_dist::WriteReq 33873 # Transaction distribution
+system.membus.trans_dist::WriteResp 33873 # Transaction distribution
+system.membus.trans_dist::Writeback 574133 # Transaction distribution
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+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq 21596881 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 21588675 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 33873 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 33873 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 6657868 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 1668053 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 1561372 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 44174 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 44175 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 2054795 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 2054795 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 27631338 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27242891 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 786774 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1184296 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 56845299 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 881615316 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1077879160 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2651280 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3722288 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 1965868044 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 493907 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 31944858 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 5.003617 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.060036 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 31829300 99.64% 99.64% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 115558 0.36% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 31944858 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 48864007000 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 3007500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 62042103256 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 39821087024 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 456077500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 719536250 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 40403 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40403 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136728 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136733 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 5 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 354272 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7492846 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 981115277 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 179046791 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 81298671 # DTB read hits
+system.cpu0.dtb.read_misses 94598 # DTB read misses
+system.cpu0.dtb.write_hits 74077534 # DTB write hits
+system.cpu0.dtb.write_misses 29691 # DTB write misses
+system.cpu0.dtb.flush_tlb 51863 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 19908 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 526 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 72449 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 4385 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 9644 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 81393269 # DTB read accesses
+system.cpu0.dtb.write_accesses 74107225 # DTB write accesses
+system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dtb.hits 155376205 # DTB hits
+system.cpu0.dtb.misses 124289 # DTB misses
+system.cpu0.dtb.accesses 155500494 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.inst_hits 433719693 # ITB inst hits
+system.cpu0.itb.inst_misses 76771 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.flush_tlb 51863 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 19908 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 526 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 53078 # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.inst_accesses 433796464 # ITB inst accesses
+system.cpu0.itb.hits 433719693 # DTB hits
+system.cpu0.itb.misses 76771 # DTB misses
+system.cpu0.itb.accesses 433796464 # DTB accesses
+system.cpu0.numCycles 51861670459 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.committedInsts 433465167 # Number of instructions committed
+system.cpu0.committedOps 509426348 # Number of ops (including micro ops) committed
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+system.cpu0.num_fp_insts 437595 # number of float instructions
+system.cpu0.num_int_register_reads 681169150 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 371166205 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 709571 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 361724 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 113513031 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 113190912 # number of times the CC registers were written
+system.cpu0.num_mem_refs 155365727 # number of memory refs
+system.cpu0.num_load_insts 81295009 # Number of load instructions
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+system.cpu0.num_busy_cycles 1600589920.967886 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.030863 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.969137 # Percentage of idle cycles
+system.cpu0.Branches 96751437 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
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+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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+system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.inst_hits 0 # ITB inst hits
+system.cpu1.dtb.inst_misses 0 # ITB inst misses
+system.cpu1.dtb.read_hits 81731723 # DTB read hits
+system.cpu1.dtb.read_misses 99102 # DTB read misses
+system.cpu1.dtb.write_hits 74078403 # DTB write hits
+system.cpu1.dtb.write_misses 30075 # DTB write misses
+system.cpu1.dtb.flush_tlb 51867 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 20925 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 515 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 72169 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 4438 # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults 9782 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 81830825 # DTB read accesses
+system.cpu1.dtb.write_accesses 74108478 # DTB write accesses
+system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dtb.hits 155810126 # DTB hits
+system.cpu1.dtb.misses 129177 # DTB misses
+system.cpu1.dtb.accesses 155939303 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.inst_hits 434297733 # ITB inst hits
+system.cpu1.itb.inst_misses 78021 # ITB inst misses
+system.cpu1.itb.read_hits 0 # DTB read hits
+system.cpu1.itb.read_misses 0 # DTB read misses
+system.cpu1.itb.write_hits 0 # DTB write hits
+system.cpu1.itb.write_misses 0 # DTB write misses
+system.cpu1.itb.flush_tlb 51867 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 20925 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 515 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 53659 # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses 0 # DTB read accesses
+system.cpu1.itb.write_accesses 0 # DTB write accesses
+system.cpu1.itb.inst_accesses 434375754 # ITB inst accesses
+system.cpu1.itb.hits 434297733 # DTB hits
+system.cpu1.itb.misses 78021 # DTB misses
+system.cpu1.itb.accesses 434375754 # DTB accesses
+system.cpu1.numCycles 51860387727 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.committedInsts 434015512 # Number of instructions committed
+system.cpu1.committedOps 509975199 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 468434913 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 458508 # Number of float alu accesses
+system.cpu1.num_func_calls 25828963 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 66119194 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 468434913 # number of integer instructions
+system.cpu1.num_fp_insts 458508 # number of float instructions
+system.cpu1.num_int_register_reads 681011171 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 371474138 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 735722 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 396908 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 113358693 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 113081851 # number of times the CC registers were written
+system.cpu1.num_mem_refs 155802990 # number of memory refs
+system.cpu1.num_load_insts 81728236 # Number of load instructions
+system.cpu1.num_store_insts 74074754 # Number of store instructions
+system.cpu1.num_idle_cycles 50263670387.895683 # Number of idle cycles
+system.cpu1.num_busy_cycles 1596717339.104316 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.030789 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.969211 # Percentage of idle cycles
+system.cpu1.Branches 96920557 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 353254188 69.23% 69.23% # Class of executed instruction
+system.cpu1.op_class::IntMult 1106936 0.22% 69.45% # Class of executed instruction
+system.cpu1.op_class::IntDiv 48650 0.01% 69.46% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 58473 0.01% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::MemRead 81728236 16.02% 85.48% # Class of executed instruction
+system.cpu1.op_class::MemWrite 74074754 14.52% 100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::total 510271279 # Class of executed instruction
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.iocache.tags.replacements 115483 # number of replacements
+system.iocache.tags.tagsinuse 10.461502 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115499 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 13154061165000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 5.844281 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 4.617221 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.365268 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.288576 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.653844 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 1039906 # Number of tag accesses
+system.iocache.tags.data_accesses 1039906 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses
+system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
+system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 5 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 5 # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8877 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
+system.iocache.overall_misses::realview.ide 8837 # number of overall misses
+system.iocache.overall_misses::total 8877 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 1908690112 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 1914175112 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide 1908690112 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 1914514112 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide 1908690112 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 1914514112 # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 106669 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 106669 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
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+system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000047 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 0.000047 # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
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+system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 215988.470295 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 215706.007663 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 215988.470295 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 215671.297961 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 215988.470295 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 215671.297961 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 51929 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 9.458834 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 106664 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses
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+system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
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+system.iocache.demand_mshr_misses::realview.ide 8837 # number of demand (read+write) MSHR misses
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+system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide 8837 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 8877 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 1449081112 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 1452642112 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6526726956 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6526726956 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 1449081112 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 1452825112 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 1449081112 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 1452825112 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163978.851646 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 163696.429119 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 163978.851646 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 163661.722654 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 163978.851646 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 163661.722654 # average overall mshr miss latency
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
+atags_addr=134217728
+boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
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+clk_domain=system.clk_domain
+dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+early_kernel_symbols=false
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+kernel_addr_check=true
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+readfile=/work/gem5.latest/tests/halt.sh
+reset_addr_64=0
+symbolfile=
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+work_end_ckpt_count=0
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+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.bridge]
+type=Bridge
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+delay=50000
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+resp_size=16
+master=system.iobus.slave[0]
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+
+[system.cf0]
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+
+[system.cf0.image]
+type=CowDiskImage
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+read_only=false
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+
+[system.cf0.image.child]
+type=RawDiskImage
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+image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
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+
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+type=SrcClockDomain
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+
+[system.cpu1.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
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+port=system.cpu1.toL2Bus.slave[3]
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+write_buffers=8
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+mem_side=system.cpu1.toL2Bus.slave[0]
+
+[system.cpu1.icache.tags]
+type=LRU
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+size=32768
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+[system.cpu1.isa]
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+id_aa64afr0_el1=0
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+id_pfr1=4113
+midr=1091551472
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+stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
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+[system.cpu1.istage2_mmu.stage2_tlb]
+type=ArmTLB
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+walker=system.cpu1.istage2_mmu.stage2_tlb.walker
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+[system.cpu1.istage2_mmu.stage2_tlb.walker]
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+num_squash_per_cycle=2
+sys=system
+port=system.cpu1.toL2Bus.slave[4]
+
+[system.cpu1.itb]
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+[system.cpu1.itb.walker]
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+system=system
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+[system.cpu1.l2cache.tags]
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+[system.cpu1.toL2Bus]
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+
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+[system.intrctrl]
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+
+[system.iobus]
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+width=8
+default=system.realview.pciconfig.pio
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+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
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+assoc=8
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+system=system
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+mem_side=system.membus.slave[3]
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+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.l2c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.l2c.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2415919103
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.l2c.cpu_side
+slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 16:01:47
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu0.isa: ISA system set to: 0x52fab00 0x52fab00
+ 0: system.cpu1.isa: ISA system set to: 0x52fab00 0x52fab00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80080000
+info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 47256535568000 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 47.256536 # Number of seconds simulated
+sim_ticks 47256535568000 # Number of ticks simulated
+final_tick 47256535568000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1272324 # Simulator instruction rate (inst/s)
+host_op_rate 1496823 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 61628014219 # Simulator tick rate (ticks/s)
+host_mem_usage 661604 # Number of bytes of host memory used
+host_seconds 766.80 # Real time elapsed on the host
+sim_insts 975621413 # Number of instructions simulated
+sim_ops 1147767763 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::realview.ide 442560 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 277248 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 420864 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 3534260 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 43570904 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 363264 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 549184 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 2429256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 46602048 # Number of bytes read from this memory
+system.physmem.bytes_read::total 98189588 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 3534260 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 2429256 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5963516 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 63972864 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 69325260 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 32048196 # Number of bytes written to this memory
+system.physmem.bytes_written::total 172176912 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 6915 # Number of read requests responded to by this memory
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+system.physmem.num_reads::cpu0.data 680817 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 5676 # Number of read requests responded to by this memory
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+system.physmem.num_reads::cpu1.data 728175 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1574766 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 999576 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 1085484 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 500754 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 2692542 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 9365 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 5867 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 8906 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 74789 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 922008 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::cpu1.itb.walker 11621 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 51406 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 986150 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2077799 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 74789 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 51406 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 126195 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1353736 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 144543 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 1466998 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 678175 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3643452 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1353736 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 153908 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 5867 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 8906 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 74789 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 2389006 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 7687 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 11621 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 51406 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 1664325 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 5721251 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 626516 # Transaction distribution
+system.membus.trans_dist::ReadResp 626516 # Transaction distribution
+system.membus.trans_dist::WriteReq 38984 # Transaction distribution
+system.membus.trans_dist::WriteResp 38984 # Transaction distribution
+system.membus.trans_dist::Writeback 999576 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 1690363 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 1690363 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 306222 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 316965 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 140146 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1165491 # Transaction distribution
+system.membus.trans_dist::ReadExResp 989253 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122908 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27744 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 8247325 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 8398069 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 231310 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 231310 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 8629379 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156015 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
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+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 263093540 # Cumulative packet size per connected master and slave (bytes)
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+system.membus.pkt_size::total 270706975 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 5022881 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 5022881 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 5022881 # Request fanout histogram
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.l2c.tags.replacements 1283901 # number of replacements
+system.l2c.tags.tagsinuse 62124.562993 # Cycle average of tags in use
+system.l2c.tags.total_refs 3275357 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 1342128 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 2.440421 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 34388.760809 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker 79.804579 # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu0.inst 3576.253573 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 7600.803334 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker 295.890565 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker 418.894238 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 2948.167503 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 12703.699250 # Average occupied blocks per requestor
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+system.l2c.tags.occ_percent::total 0.947946 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023 419 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024 57808 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::1 13 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2 14 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3 33 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4 357 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 2958 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3 4258 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4 50148 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023 0.006393 # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024 0.882080 # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses 65498174 # Number of tag accesses
+system.l2c.tags.data_accesses 65498174 # Number of data accesses
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+system.l2c.ReadReq_hits::total 2227532 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 2009484 # number of Writeback hits
+system.l2c.Writeback_hits::total 2009484 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 14899 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 10552 # number of UpgradeReq hits
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+system.l2c.Writeback_accesses::writebacks 2009484 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 2009484 # number of Writeback accesses(hits+misses)
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+system.l2c.ReadExReq_accesses::total 1308142 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 9960 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 10101 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 505302 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 1534335 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 10427 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 11405 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 481921 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 1507563 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 4071014 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 9960 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 10101 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 505302 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 1534335 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 10427 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 11405 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 481921 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 1507563 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 4071014 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.434940 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.651025 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.103956 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.219628 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.544356 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.752389 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.078747 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.265088 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.193762 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.786874 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.831378 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.807895 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.854716 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.866366 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 0.860350 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.757251 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.781778 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.769467 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.434940 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.651025 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.103956 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.449699 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.544356 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker 0.752389 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.078747 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.488390 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.378754 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.434940 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.651025 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.103956 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.449699 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.544356 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker 0.752389 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.078747 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.488390 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.378754 # miss rate for overall accesses
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.writebacks::writebacks 999576 # number of writebacks
+system.l2c.writebacks::total 999576 # number of writebacks
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq 3538474 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 3538474 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38984 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38984 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 2009484 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 1583635 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 1583635 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 314351 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 319528 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 633879 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 1484380 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 1484380 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9022261 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7545927 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 16568188 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 295040248 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 251523687 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 546563935 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 117027 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 9283255 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.012458 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.110920 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 9167600 98.75% 98.75% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 115655 1.25% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 9283255 # Request fanout histogram
+system.iobus.trans_dist::ReadReq 40365 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40365 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136744 # Transaction distribution
+system.iobus.trans_dist::WriteResp 30016 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47974 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122908 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231230 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231230 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 354218 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47994 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 156015 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338936 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7338936 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7497037 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 91995299 # DTB read hits
+system.cpu0.dtb.read_misses 88130 # DTB read misses
+system.cpu0.dtb.write_hits 85085254 # DTB write hits
+system.cpu0.dtb.write_misses 36248 # DTB write misses
+system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 36322 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 5755 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 10368 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 92083429 # DTB read accesses
+system.cpu0.dtb.write_accesses 85121502 # DTB write accesses
+system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dtb.hits 177080553 # DTB hits
+system.cpu0.dtb.misses 124378 # DTB misses
+system.cpu0.dtb.accesses 177204931 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.inst_hits 494454438 # ITB inst hits
+system.cpu0.itb.inst_misses 60733 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
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+system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu0.l2cache.writebacks::writebacks 1036299 # number of writebacks
+system.cpu0.l2cache.writebacks::total 1036299 # number of writebacks
+system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.dcache.tags.replacements 6244160 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 501.112038 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 170764768 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 6244672 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 27.345675 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 35630500 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.112038 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978734 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.978734 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses 360574457 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 360574457 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 85562109 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 85562109 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 80321665 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 80321665 # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214579 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 214579 # number of SoftPFReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 1082882 # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::total 1082882 # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2079487 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 2079487 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2037790 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 2037790 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 165883774 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 165883774 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 166098353 # number of overall hits
+system.cpu0.dcache.overall_hits::total 166098353 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 3290675 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 3290675 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1472676 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 1472676 # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 774388 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total 774388 # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 118159 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 118159 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158665 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 158665 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 4763351 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 4763351 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 5537739 # number of overall misses
+system.cpu0.dcache.overall_misses::total 5537739 # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 88852784 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 88852784 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 81794341 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 81794341 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 988967 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total 988967 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1082882 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::total 1082882 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2197646 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 2197646 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2196455 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 2196455 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 170647125 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 170647125 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 171636092 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 171636092 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037035 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.037035 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018005 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.018005 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.783027 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.783027 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053766 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053766 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072237 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072237 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027913 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.027913 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032264 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.032264 # miss rate for overall accesses
+system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes 1082882 # number of fast writes performed
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks 3700491 # number of writebacks
+system.cpu0.dcache.writebacks::total 3700491 # number of writebacks
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.toL2Bus.trans_dist::ReadReq 10282171 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 10282171 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 33363 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 33363 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 3700491 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1082882 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 1082882 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 129573 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158665 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 288238 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1343103 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1343103 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11045230 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17628413 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 362824 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 723538 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 29760005 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 350859860 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 660019940 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1451296 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2894152 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 1015225248 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 3571522 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 20011038 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 5.169428 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.375130 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5 16620607 83.06% 83.06% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6 3390431 16.94% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 20011038 # Request fanout histogram
+system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.inst_hits 0 # ITB inst hits
+system.cpu1.dtb.inst_misses 0 # ITB inst misses
+system.cpu1.dtb.read_hits 90837844 # DTB read hits
+system.cpu1.dtb.read_misses 112429 # DTB read misses
+system.cpu1.dtb.write_hits 81788331 # DTB write hits
+system.cpu1.dtb.write_misses 32675 # DTB write misses
+system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 44635 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 4658 # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults 11499 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 90950273 # DTB read accesses
+system.cpu1.dtb.write_accesses 81821006 # DTB write accesses
+system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dtb.hits 172626175 # DTB hits
+system.cpu1.dtb.misses 145104 # DTB misses
+system.cpu1.dtb.accesses 172771279 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.inst_hits 481654104 # ITB inst hits
+system.cpu1.itb.inst_misses 61573 # ITB inst misses
+system.cpu1.itb.read_hits 0 # DTB read hits
+system.cpu1.itb.read_misses 0 # DTB read misses
+system.cpu1.itb.write_hits 0 # DTB write hits
+system.cpu1.itb.write_misses 0 # DTB write misses
+system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 31343 # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses 0 # DTB read accesses
+system.cpu1.itb.write_accesses 0 # DTB write accesses
+system.cpu1.itb.inst_accesses 481715677 # ITB inst accesses
+system.cpu1.itb.hits 481654104 # DTB hits
+system.cpu1.itb.misses 61573 # DTB misses
+system.cpu1.itb.accesses 481715677 # DTB accesses
+system.cpu1.numCycles 94513077342 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.committedInsts 481400602 # Number of instructions committed
+system.cpu1.committedOps 566525898 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 519925383 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 376275 # Number of float alu accesses
+system.cpu1.num_func_calls 28379756 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 73707085 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 519925383 # number of integer instructions
+system.cpu1.num_fp_insts 376275 # number of float instructions
+system.cpu1.num_int_register_reads 767883598 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 413862248 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 612543 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 304496 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 127269525 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 126984366 # number of times the CC registers were written
+system.cpu1.num_mem_refs 172747819 # number of memory refs
+system.cpu1.num_load_insts 90937276 # Number of load instructions
+system.cpu1.num_store_insts 81810543 # Number of store instructions
+system.cpu1.num_idle_cycles 93946237892.041718 # Number of idle cycles
+system.cpu1.num_busy_cycles 566839449.958294 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.005997 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.994003 # Percentage of idle cycles
+system.cpu1.Branches 107245418 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 392850961 69.31% 69.31% # Class of executed instruction
+system.cpu1.op_class::IntMult 1138465 0.20% 69.51% # Class of executed instruction
+system.cpu1.op_class::IntDiv 60868 0.01% 69.52% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction
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+system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 500753 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::total 500753 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2208308 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 2208308 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2206991 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 2206991 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 166834845 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 166834845 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 167813427 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 167813427 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038370 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.038370 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018321 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.018321 # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.807513 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.807513 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066070 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066070 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072888 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.072888 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028865 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.028865 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033406 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.033406 # miss rate for overall accesses
+system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes 500753 # number of fast writes performed
+system.cpu1.dcache.cache_copies 0 # number of cache copies performed
+system.cpu1.dcache.writebacks::writebacks 3626404 # number of writebacks
+system.cpu1.dcache.writebacks::total 3626404 # number of writebacks
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.toL2Bus.trans_dist::ReadReq 9718709 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 9718709 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 5621 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 5621 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 3626404 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 500753 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 500753 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 134493 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 160863 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 295356 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1314492 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1314492 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9610878 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16476244 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368094 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 841050 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 27296266 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 307540296 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 623681695 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1472376 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3364200 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 936058567 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 4159575 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 19448735 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 5.205617 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.404152 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5 15449740 79.44% 79.44% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6 3998995 20.56% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 19448735 # Request fanout histogram
+system.iocache.tags.replacements 115596 # number of replacements
+system.iocache.tags.tagsinuse 11.294855 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115612 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.848747 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 7.446108 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.240547 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.465382 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.705928 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 1040892 # Number of tag accesses
+system.iocache.tags.data_accesses 1040892 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 106728 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 106728 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8887 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8924 # number of ReadReq misses
+system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
+system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
+system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8887 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8927 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
+system.iocache.overall_misses::realview.ide 8887 # number of overall misses
+system.iocache.overall_misses::total 8927 # number of overall misses
+system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8887 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8924 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8887 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8927 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8887 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8927 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 106728 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
+atags_addr=134217728
+boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
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+have_generic_timer=false
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+have_virtualization=false
+highest_el_is_64=false
+init_param=0
+kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel_addr_check=true
+load_addr_mask=268435455
+load_offset=2147483648
+machine_type=VExpress_EMM64
+mem_mode=atomic
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.vram system.realview.nvmem
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+phys_addr_range_64=40
+readfile=/work/gem5.latest/tests/halt.sh
+reset_addr_64=0
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.bridge]
+type=Bridge
+clk_domain=system.clk_domain
+delay=50000
+eventq_index=0
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+eventq_index=0
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+eventq_index=0
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+eventq_index=0
+image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
+dtb=system.cpu.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+tlb=system.cpu.dtb
+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[5]
+
+[system.cpu.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[3]
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=1
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[4]
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+use_default_range=true
+width=8
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
+eventq_index=0
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2415919103
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 16:00:57
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-atomic
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu.isa: ISA system set to: 0x54cdb00 0x54cdb00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80080000
+info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 51111167186000 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 51.111167 # Number of seconds simulated
+sim_ticks 51111167186000 # Number of ticks simulated
+final_tick 51111167186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1374172 # Simulator instruction rate (inst/s)
+host_op_rate 1614949 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 71508211345 # Simulator tick rate (ticks/s)
+host_mem_usage 650720 # Number of bytes of host memory used
+host_seconds 714.76 # Real time elapsed on the host
+sim_insts 982202425 # Number of instructions simulated
+sim_ops 1154300154 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::realview.ide 441600 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 674240 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 976256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 5095732 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 90778056 # Number of bytes read from this memory
+system.physmem.bytes_read::total 97965884 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 5095732 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5095732 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 65987904 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 101336100 # Number of bytes written to this memory
+system.physmem.bytes_written::total 174150500 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 6900 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 10535 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 15254 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 120028 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1418420 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1571137 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1031061 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data 1585628 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 2723353 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 8640 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 13192 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 19101 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 99699 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1776090 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1916722 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 99699 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 99699 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1291066 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 133562 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1982661 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3407289 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1291066 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 142202 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 13192 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 19101 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 99699 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3758751 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 5324010 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 581631 # Transaction distribution
+system.membus.trans_dist::ReadResp 581631 # Transaction distribution
+system.membus.trans_dist::WriteReq 33712 # Transaction distribution
+system.membus.trans_dist::WriteResp 33712 # Transaction distribution
+system.membus.trans_dist::Writeback 1031061 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 1689719 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 1689719 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 40041 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 40042 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1025075 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1025075 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122798 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7410875 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7540385 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 231034 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 231034 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 7771419 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155928 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 264848480 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 265017848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7392896 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7392896 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 272410744 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 4290796 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 4290796 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 4290796 # Request fanout histogram
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
+system.iobus.trans_dist::ReadReq 40295 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40295 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136621 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29957 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47916 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122798 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353832 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47936 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155928 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7492262 # Cumulative packet size per connected master and slave (bytes)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 183545113 # DTB read hits
+system.cpu.dtb.read_misses 195347 # DTB read misses
+system.cpu.dtb.write_hits 167775000 # DTB write hits
+system.cpu.dtb.write_misses 71236 # DTB write misses
+system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 82503 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 9078 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 183740460 # DTB read accesses
+system.cpu.dtb.write_accesses 167846236 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 351320113 # DTB hits
+system.cpu.dtb.misses 266583 # DTB misses
+system.cpu.dtb.accesses 351586696 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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+system.cpu.l2cache.writebacks::total 1031061 # number of writebacks
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements 11606184 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 339855980 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 11606696 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 29.281027 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 1417457465 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1417457465 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 171111123 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 171111123 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 159073587 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 159073587 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 424480 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 424480 # number of SoftPFReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 1583055 # number of WriteInvalidateReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::total 1583055 # number of WriteInvalidateReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303648 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 4303648 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 4555648 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 4555648 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 330184710 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 330184710 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 330609190 # number of overall hits
+system.cpu.dcache.overall_hits::total 330609190 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 6002953 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 6002953 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2568202 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2568202 # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data 1586188 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 1586188 # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 253804 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 253804 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 8571155 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 8571155 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 10157343 # number of overall misses
+system.cpu.dcache.overall_misses::total 10157343 # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data 177114076 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 177114076 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 161641789 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 161641789 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010668 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 2010668 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583055 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::total 1583055 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557452 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 4557452 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555649 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 4555649 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 338755865 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 338755865 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 340766533 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 340766533 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033893 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.033893 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788886 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.788886 # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055690 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055690 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025302 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.025302 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.029807 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.029807 # miss rate for overall accesses
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 1583055 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 7859784 # number of writebacks
+system.cpu.dcache.writebacks::total 7859784 # number of writebacks
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 23338761 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 23338761 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 33712 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 33712 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 7859784 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1583055 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1583055 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 51208 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 51209 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 2516994 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 2516994 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28617810 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31982828 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548400 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 62907246 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 913182420 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1267567780 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193600 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 2189976632 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 116124 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 35388588 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5.003264 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.057040 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 35273071 99.67% 99.67% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 115517 0.33% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 35388588 # Request fanout histogram
+system.iocache.tags.replacements 115459 # number of replacements
+system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor
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+system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 1039650 # Number of tag accesses
+system.iocache.tags.data_accesses 1039650 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses
+system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
+system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
+system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8853 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
+system.iocache.overall_misses::realview.ide 8813 # number of overall misses
+system.iocache.overall_misses::total 8853 # number of overall misses
+system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 106664 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
+atags_addr=134217728
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+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+early_kernel_symbols=false
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+gic_cpu_addr=738205696
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+highest_el_is_64=false
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+kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel_addr_check=true
+load_addr_mask=268435455
+load_offset=2147483648
+machine_type=VExpress_EMM64
+mem_mode=timing
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.nvmem system.realview.vram
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+phys_addr_range_64=40
+readfile=/work/gem5.latest/tests/halt.sh
+reset_addr_64=0
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.bridge]
+type=Bridge
+clk_domain=system.clk_domain
+delay=50000
+eventq_index=0
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+eventq_index=0
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+eventq_index=0
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+eventq_index=0
+image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu0]
+type=TimingSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu0.dstage2_mmu
+dtb=system.cpu0.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+istage2_mmu=system.cpu0.istage2_mmu
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+workload=
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=6
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.dcache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=16
+cpu_side=system.cpu0.dcache_port
+mem_side=system.cpu0.toL2Bus.slave[1]
+
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu0.dstage2_mmu]
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+
+[system.cpu0.dstage2_mmu.stage2_tlb]
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+size=32
+walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu0.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
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+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu0.toL2Bus.slave[5]
+
+[system.cpu0.dtb]
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+is_stage2=false
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
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+num_squash_per_cycle=2
+sys=system
+port=system.cpu0.toL2Bus.slave[3]
+
+[system.cpu0.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
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+forward_snoops=true
+hit_latency=1
+is_top_level=true
+max_miss_count=0
+mshrs=2
+prefetch_on_access=false
+prefetcher=Null
+response_latency=1
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.icache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.cpu0.toL2Bus.slave[0]
+
+[system.cpu0.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=1
+sequential_access=false
+size=32768
+
+[system.cpu0.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu0.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu0.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+tlb=system.cpu0.itb
+
+[system.cpu0.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
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+is_stage2=true
+size=32
+walker=system.cpu0.istage2_mmu.stage2_tlb.walker
+
+[system.cpu0.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu0.toL2Bus.slave[4]
+
+[system.cpu0.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu0.itb.walker
+
+[system.cpu0.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu0.toL2Bus.slave[2]
+
+[system.cpu0.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu0.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu0.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu0.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu0.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu0.l2cache.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+
+[system.cpu0.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu1]
+type=TimingSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=1
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu1.dstage2_mmu
+dtb=system.cpu1.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
+istage2_mmu=system.cpu1.istage2_mmu
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu1.tracer
+workload=
+dcache_port=system.cpu1.dcache.cpu_side
+icache_port=system.cpu1.icache.cpu_side
+
+[system.cpu1.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=6
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu1.dcache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=16
+cpu_side=system.cpu1.dcache_port
+mem_side=system.cpu1.toL2Bus.slave[1]
+
+[system.cpu1.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu1.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+tlb=system.cpu1.dtb
+
+[system.cpu1.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu1.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu1.toL2Bus.slave[5]
+
+[system.cpu1.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu1.dtb.walker
+
+[system.cpu1.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu1.toL2Bus.slave[3]
+
+[system.cpu1.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=1
+is_top_level=true
+max_miss_count=0
+mshrs=2
+prefetch_on_access=false
+prefetcher=Null
+response_latency=1
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu1.icache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.icache_port
+mem_side=system.cpu1.toL2Bus.slave[0]
+
+[system.cpu1.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=1
+sequential_access=false
+size=32768
+
+[system.cpu1.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu1.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu1.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+tlb=system.cpu1.itb
+
+[system.cpu1.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu1.istage2_mmu.stage2_tlb.walker
+
+[system.cpu1.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu1.toL2Bus.slave[4]
+
+[system.cpu1.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu1.toL2Bus.slave[2]
+
+[system.cpu1.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu1.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu1.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu1.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu1.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu1.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu1.l2cache.cpu_side
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+
+[system.cpu1.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+use_default_range=true
+width=8
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
+eventq_index=0
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.l2c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.l2c.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=2147483648:2415919103
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
+tWTR=7500
+tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.l2c.cpu_side
+slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 16:01:57
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu0.isa: ISA system set to: 0x5b5eb00 0x5b5eb00
+ 0: system.cpu1.isa: ISA system set to: 0x5b5eb00 0x5b5eb00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80080000
+info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 47438274662000 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 47.438275 # Number of seconds simulated
+sim_ticks 47438274662000 # Number of ticks simulated
+final_tick 47438274662000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 649244 # Simulator instruction rate (inst/s)
+host_op_rate 763603 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 34889420828 # Simulator tick rate (ticks/s)
+host_mem_usage 811016 # Number of bytes of host memory used
+host_seconds 1359.68 # Real time elapsed on the host
+sim_insts 882760938 # Number of instructions simulated
+sim_ops 1038251286 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::realview.ide 477376 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 221952 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 405952 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 701748 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 13046680 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 27196672 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 278976 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 430208 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 568824 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 13928160 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 27822464 # Number of bytes read from this memory
+system.physmem.bytes_read::total 85079012 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 701748 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 568824 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1270572 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 44376640 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 54965772 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 45117316 # Number of bytes written to this memory
+system.physmem.bytes_written::total 151290320 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 7459 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 3468 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 6343 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 51372 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 203876 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 424948 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 4359 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 6722 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 8976 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 217642 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 434726 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1369891 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 693385 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 861117 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 704959 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 2366189 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 10063 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 4679 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 8557 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 14793 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 275024 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 573307 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 5881 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 9069 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 11991 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 293606 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 586498 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1793468 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 14793 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 11991 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 26784 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 935461 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 143989 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 1158680 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 951074 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3189204 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 935461 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 154052 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 4679 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 8557 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 14793 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1433704 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 573307 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 5881 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 9069 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 11991 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 1244680 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 586498 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4982671 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1369891 # Number of read requests accepted
+system.physmem.writeReqs 2366189 # Number of write requests accepted
+system.physmem.readBursts 1369891 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 2366189 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 87382976 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 290048 # Total number of bytes read from write queue
+system.physmem.bytesWritten 145690880 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 85079012 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 151290320 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 4532 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 89741 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 95337 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 80179 # Per bank write bursts
+system.physmem.perBankRdBursts::1 81898 # Per bank write bursts
+system.physmem.perBankRdBursts::2 76695 # Per bank write bursts
+system.physmem.perBankRdBursts::3 88857 # Per bank write bursts
+system.physmem.perBankRdBursts::4 82614 # Per bank write bursts
+system.physmem.perBankRdBursts::5 89869 # Per bank write bursts
+system.physmem.perBankRdBursts::6 79228 # Per bank write bursts
+system.physmem.perBankRdBursts::7 87605 # Per bank write bursts
+system.physmem.perBankRdBursts::8 77754 # Per bank write bursts
+system.physmem.perBankRdBursts::9 127975 # Per bank write bursts
+system.physmem.perBankRdBursts::10 81231 # Per bank write bursts
+system.physmem.perBankRdBursts::11 85621 # Per bank write bursts
+system.physmem.perBankRdBursts::12 74411 # Per bank write bursts
+system.physmem.perBankRdBursts::13 85967 # Per bank write bursts
+system.physmem.perBankRdBursts::14 83368 # Per bank write bursts
+system.physmem.perBankRdBursts::15 82087 # Per bank write bursts
+system.physmem.perBankWrBursts::0 134695 # Per bank write bursts
+system.physmem.perBankWrBursts::1 125793 # Per bank write bursts
+system.physmem.perBankWrBursts::2 142260 # Per bank write bursts
+system.physmem.perBankWrBursts::3 126417 # Per bank write bursts
+system.physmem.perBankWrBursts::4 155026 # Per bank write bursts
+system.physmem.perBankWrBursts::5 152020 # Per bank write bursts
+system.physmem.perBankWrBursts::6 183109 # Per bank write bursts
+system.physmem.perBankWrBursts::7 140837 # Per bank write bursts
+system.physmem.perBankWrBursts::8 128222 # Per bank write bursts
+system.physmem.perBankWrBursts::9 141420 # Per bank write bursts
+system.physmem.perBankWrBursts::10 135722 # Per bank write bursts
+system.physmem.perBankWrBursts::11 146309 # Per bank write bursts
+system.physmem.perBankWrBursts::12 139215 # Per bank write bursts
+system.physmem.perBankWrBursts::13 127398 # Per bank write bursts
+system.physmem.perBankWrBursts::14 153454 # Per bank write bursts
+system.physmem.perBankWrBursts::15 144523 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
+system.physmem.totGap 47438271681000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 43195 # Read request sizes (log2)
+system.physmem.readPktSize::3 37 # Read request sizes (log2)
+system.physmem.readPktSize::4 5 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 1326654 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 2 # Write request sizes (log2)
+system.physmem.writePktSize::3 2601 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 2363586 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 850336 # What read queue length does an incoming req see
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+system.physmem.wrQLenPdf::42 324 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::52 178 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 179 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::55 131 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 114 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 87 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 73 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 831449 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 280.321107 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 152.348246 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 337.173071 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 412387 49.60% 49.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 160013 19.25% 68.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 57469 6.91% 75.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 29190 3.51% 79.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 24961 3.00% 82.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 16130 1.94% 84.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 12424 1.49% 85.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 12438 1.50% 87.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 106437 12.80% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 831449 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 117879 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 11.582360 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 193.016425 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 117876 100.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::20480-22527 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 117879 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 117879 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.311497 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.988433 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 4.874271 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 75351 63.92% 63.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 36700 31.13% 95.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 3007 2.55% 97.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 902 0.77% 98.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 786 0.67% 99.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 199 0.17% 99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 149 0.13% 99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 77 0.07% 99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 81 0.07% 99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 16 0.01% 99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 14 0.01% 99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 14 0.01% 99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 396 0.34% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 29 0.02% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 39 0.03% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 22 0.02% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 47 0.04% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 4 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 10 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 4 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 6 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 1 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 15 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 4 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 117879 # Writes before turning the bus around for reads
+system.physmem.totQLat 39355914512 # Total ticks spent queuing
+system.physmem.totMemAccLat 64956395762 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 6826795000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 28824.59 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 47574.59 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.84 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 3.07 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.79 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.19 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.04 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.35 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 26.79 # Average write queue length when enqueuing
+system.physmem.readRowHits 1064531 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1745793 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 77.97 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 76.69 # Row buffer hit rate for writes
+system.physmem.avgGap 12697338.30 # Average gap between requests
+system.physmem.pageHitRate 77.17 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 45390521349500 # Time in different power states
+system.physmem.memoryStateTime::REF 1584068200000 # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem.memoryStateTime::ACT 463683887500 # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem.actEnergy::0 3148966800 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 3136780080 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 1718186250 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 1711536750 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 5202085200 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 5447566800 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 7517817360 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 7233384240 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 3098437399200 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 3098437399200 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 1260445205745 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 1262996298315 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 27357310364250 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 27355072563750 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 31733780024805 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 31734035529135 # Total energy per rank (pJ)
+system.physmem.averagePower::0 668.948883 # Core power per rank (mW)
+system.physmem.averagePower::1 668.954269 # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2246197250 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1998253750 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5835000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3361097750 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 7611383750 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2007075001 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3246096000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 5253171001 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2246197250 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4005328751 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5835000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6607193750 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 12864554751 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.367490 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.618890 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.059448 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.183764 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.221983 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.407041 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.592142 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.057956 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.184318 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.210468 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.201920 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.604611 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.558081 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.579630 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.589898 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.592581 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.591345 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.614254 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.588064 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.601221 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.367490 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.618890 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.059448 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.249421 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.221983 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.407041 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.592142 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.057956 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.239009 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.210468 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.218401 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.367490 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.618890 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.059448 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.249421 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.221983 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.407041 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.592142 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.057956 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.239009 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.210468 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.218401 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67475.561419 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 67697.618004 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 75401.371781 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68662.169759 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92779.791130 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66479.810507 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 66432.719726 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 76896.166291 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68748.745549 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93742.815325 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 86797.091849 # average ReadReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10155.620990 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10137.957643 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10146.490520 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10189.160479 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10233.726378 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10213.251811 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60820.714391 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60469.605176 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 60649.816349 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67475.561419 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67697.618004 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75401.371781 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 65716.855474 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92779.791130 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66479.810507 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 66432.719726 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76896.166291 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65989.421912 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93742.815325 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 83826.075199 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67475.561419 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67697.618004 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75401.371781 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65716.855474 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92779.791130 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66479.810507 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 66432.719726 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76896.166291 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65989.421912 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93742.815325 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 83826.075199 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq 6645186 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 6637629 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38160 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38160 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 1982686 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 1670210 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 1563473 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 355152 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 313787 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 668939 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 102 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 297718 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 297718 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9432330 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9652916 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 19085246 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 302653655 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 312342176 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 614995831 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 1425200 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 11183456 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.010347 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.101194 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 11067738 98.97% 98.97% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 115718 1.03% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 11183456 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 19814172733 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 6396000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 15605521398 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 16621378743 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 40465 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40465 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136732 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136786 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 54 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48150 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 123084 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231338 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231338 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 354502 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48170 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 156191 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339368 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7339368 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7497645 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36603000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 981958721 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 93029000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 179341978 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 81279666 # DTB read hits
+system.cpu0.dtb.read_misses 78948 # DTB read misses
+system.cpu0.dtb.write_hits 73742535 # DTB write hits
+system.cpu0.dtb.write_misses 27290 # DTB write misses
+system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 31886 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 3595 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 8523 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 81358614 # DTB read accesses
+system.cpu0.dtb.write_accesses 73769825 # DTB write accesses
+system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dtb.hits 155022201 # DTB hits
+system.cpu0.dtb.misses 106238 # DTB misses
+system.cpu0.dtb.accesses 155128439 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.inst_hits 432012599 # ITB inst hits
+system.cpu0.itb.inst_misses 54786 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 22623 # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.inst_accesses 432067385 # ITB inst accesses
+system.cpu0.itb.hits 432012599 # DTB hits
+system.cpu0.itb.misses 54786 # DTB misses
+system.cpu0.itb.accesses 432067385 # DTB accesses
+system.cpu0.numCycles 94876549324 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.committedInsts 431769250 # Number of instructions committed
+system.cpu0.committedOps 507110651 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 465722099 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 423380 # Number of float alu accesses
+system.cpu0.num_func_calls 25579239 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 65525116 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 465722099 # number of integer instructions
+system.cpu0.num_fp_insts 423380 # number of float instructions
+system.cpu0.num_int_register_reads 674979358 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 369311745 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 705560 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 308536 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 112703400 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 112387692 # number of times the CC registers were written
+system.cpu0.num_mem_refs 155012297 # number of memory refs
+system.cpu0.num_load_insts 81273219 # Number of load instructions
+system.cpu0.num_store_insts 73739078 # Number of store instructions
+system.cpu0.num_idle_cycles 93821929037.552032 # Number of idle cycles
+system.cpu0.num_busy_cycles 1054620286.447978 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.011116 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.988884 # Percentage of idle cycles
+system.cpu0.Branches 96363585 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 351187949 69.21% 69.21% # Class of executed instruction
+system.cpu0.op_class::IntMult 1094457 0.22% 69.43% # Class of executed instruction
+system.cpu0.op_class::IntDiv 58568 0.01% 69.44% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.44% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 43852 0.01% 69.45% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction
+system.cpu0.op_class::MemRead 81273219 16.02% 85.47% # Class of executed instruction
+system.cpu0.op_class::MemWrite 73739078 14.53% 100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu0.op_class::total 507397124 # Class of executed instruction
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 5117 # number of quiesce instructions executed
+system.cpu0.icache.tags.replacements 4835795 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.921057 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 427176292 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 4836307 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 88.326959 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 24248022750 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.921057 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999846 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.999846 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses 868861505 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 868861505 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 427176292 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 427176292 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 427176292 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 427176292 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 427176292 # number of overall hits
+system.cpu0.icache.overall_hits::total 427176292 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 4836307 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 4836307 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 4836307 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 4836307 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 4836307 # number of overall misses
+system.cpu0.icache.overall_misses::total 4836307 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 42021880066 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 42021880066 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 42021880066 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 42021880066 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 42021880066 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 42021880066 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 432012599 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 432012599 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 432012599 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 432012599 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 432012599 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 432012599 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011195 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.011195 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011195 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.011195 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011195 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.011195 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8688.836351 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 8688.836351 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8688.836351 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 8688.836351 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8688.836351 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 8688.836351 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4836307 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 4836307 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 4836307 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 4836307 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 4836307 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 4836307 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 34764760966 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 34764760966 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 34764760966 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 34764760966 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 34764760966 # number of overall MSHR miss cycles
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+system.cpu0.dcache.tags.avg_refs 28.300990 # Average number of references to valid blocks.
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+system.cpu0.dcache.tags.data_accesses 315346998 # Number of data accesses
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+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027826 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.027826 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031738 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.031738 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14534.036584 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14534.036584 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17640.531216 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 17640.531216 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14532.695822 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14532.695822 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21352.315148 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21352.315148 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15498.094595 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 15498.094595 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13515.893124 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 13515.893124 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes 858515 # number of fast writes performed
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks 2894821 # number of writebacks
+system.cpu0.dcache.writebacks::total 2894821 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28163 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 28163 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21327 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 21327 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41518 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41518 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 49490 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 49490 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 49490 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 49490 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2840027 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 2840027 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1269307 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 1269307 # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 608681 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 608681 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104015 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104015 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 185850 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 185850 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 4109334 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 4109334 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 4718015 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 4718015 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 34673571058 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 34673571058 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 19854321886 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 19854321886 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13611528726 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13611528726 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 38259906745 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 38259906745 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1241876461 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1241876461 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3588911169 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3588911169 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1889000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1889000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 54527892944 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 54527892944 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 68139421670 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 68139421670 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2380477468 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2380477468 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2403593708 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2403593708 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4784071176 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4784071176 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036163 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036163 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017897 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017897 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.768722 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.768722 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053668 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.053668 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095944 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095944 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027495 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.027495 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031401 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.031401 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12208.887823 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12208.887823 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15641.859602 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15641.859602 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22362.335486 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22362.335486 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11939.397789 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11939.397789 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19310.794560 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19310.794560 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13269.277441 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13269.277441 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14442.391911 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14442.391911 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.toL2Bus.trans_dist::ReadReq 12330313 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 9009509 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 16126 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 16126 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 2894821 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 3465295 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1670210 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 858515 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 371533 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 344881 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 439023 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1234519 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1094177 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 9758864 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 14862906 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 296442 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 542592 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 25460804 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 309696148 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 543504195 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1062208 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1873320 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 856135871 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 8448176 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 22253887 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 5.367543 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.482136 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5 14074632 63.25% 63.25% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6 8179255 36.75% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 22253887 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 10836211781 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 180026995 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer0.occupancy 7309068550 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer1.occupancy 7654516797 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer2.occupancy 164187799 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer3.occupancy 308745047 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.inst_hits 0 # ITB inst hits
+system.cpu1.dtb.inst_misses 0 # ITB inst misses
+system.cpu1.dtb.read_hits 85169560 # DTB read hits
+system.cpu1.dtb.read_misses 81568 # DTB read misses
+system.cpu1.dtb.write_hits 77252621 # DTB write hits
+system.cpu1.dtb.write_misses 28177 # DTB write misses
+system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 42405 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 4822 # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults 11145 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 85251128 # DTB read accesses
+system.cpu1.dtb.write_accesses 77280798 # DTB write accesses
+system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dtb.hits 162422181 # DTB hits
+system.cpu1.dtb.misses 109745 # DTB misses
+system.cpu1.dtb.accesses 162531926 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.inst_hits 451299133 # ITB inst hits
+system.cpu1.itb.inst_misses 60868 # ITB inst misses
+system.cpu1.itb.read_hits 0 # DTB read hits
+system.cpu1.itb.read_misses 0 # DTB read misses
+system.cpu1.itb.write_hits 0 # DTB write hits
+system.cpu1.itb.write_misses 0 # DTB write misses
+system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 29689 # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses 0 # DTB read accesses
+system.cpu1.itb.write_accesses 0 # DTB write accesses
+system.cpu1.itb.inst_accesses 451360001 # ITB inst accesses
+system.cpu1.itb.hits 451299133 # DTB hits
+system.cpu1.itb.misses 60868 # DTB misses
+system.cpu1.itb.accesses 451360001 # DTB accesses
+system.cpu1.numCycles 94876549324 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.committedInsts 450991688 # Number of instructions committed
+system.cpu1.committedOps 531140635 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 488008709 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 470535 # Number of float alu accesses
+system.cpu1.num_func_calls 27052635 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 68722135 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 488008709 # number of integer instructions
+system.cpu1.num_fp_insts 470535 # number of float instructions
+system.cpu1.num_int_register_reads 711965253 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 387496587 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 748074 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 424948 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 118082190 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 117761356 # number of times the CC registers were written
+system.cpu1.num_mem_refs 162414438 # number of memory refs
+system.cpu1.num_load_insts 85168501 # Number of load instructions
+system.cpu1.num_store_insts 77245937 # Number of store instructions
+system.cpu1.num_idle_cycles 93789094629.720032 # Number of idle cycles
+system.cpu1.num_busy_cycles 1087454694.279977 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.011462 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.988538 # Percentage of idle cycles
+system.cpu1.Branches 100614893 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 367777606 69.20% 69.20% # Class of executed instruction
+system.cpu1.op_class::IntMult 1128259 0.21% 69.42% # Class of executed instruction
+system.cpu1.op_class::IntDiv 59926 0.01% 69.43% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 67918 0.01% 69.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction
+system.cpu1.op_class::MemRead 85168501 16.03% 85.47% # Class of executed instruction
+system.cpu1.op_class::MemWrite 77245937 14.53% 100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::total 531448189 # Class of executed instruction
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 13727 # number of quiesce instructions executed
+system.cpu1.icache.tags.replacements 5018265 # number of replacements
+system.cpu1.icache.tags.tagsinuse 496.292950 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 446280351 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 5018777 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 88.922132 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 8374030789000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.292950 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969322 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.969322 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1 272 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses 907617048 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 907617048 # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst 446280351 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 446280351 # number of ReadReq hits
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+system.cpu1.icache.overall_hits::cpu1.inst 446280351 # number of overall hits
+system.cpu1.icache.overall_hits::total 446280351 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 5018782 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 5018782 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 5018782 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 5018782 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 5018782 # number of overall misses
+system.cpu1.icache.overall_misses::total 5018782 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 43828213410 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 43828213410 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 43828213410 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 43828213410 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 43828213410 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 43828213410 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 451299133 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 451299133 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 451299133 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 451299133 # number of demand (read+write) accesses
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+system.cpu1.icache.overall_accesses::total 451299133 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011121 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.011121 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011121 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.011121 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011121 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.011121 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8732.838647 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 8732.838647 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8732.838647 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 8732.838647 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8732.838647 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 8732.838647 # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes 0 # number of fast writes performed
+system.cpu1.icache.cache_copies 0 # number of cache copies performed
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5018782 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 5018782 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 5018782 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 5018782 # number of demand (read+write) MSHR misses
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+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 36297023628 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 36297023628 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 36297023628 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 36297023628 # number of demand (read+write) MSHR miss cycles
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+system.cpu1.icache.overall_mshr_miss_latency::total 36297023628 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8745500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8745500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8745500 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total 8745500 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011121 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011121 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011121 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.011121 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011121 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.011121 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7232.237548 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7232.237548 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7232.237548 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 7232.237548 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7232.237548 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 7232.237548 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 46849798 # number of hwpf identified
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 849083 # number of hwpf that were already in mshr
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 43478767 # number of hwpf that were already in the cache
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8509 # number of hwpf that were already in the prefetch queue
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 498 # number of hwpf removed because MSHR allocated
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2512941 # number of hwpf issued
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4003522 # number of hwpf spanning a virtual page
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu1.l2cache.tags.replacements 3186327 # number of replacements
+system.cpu1.l2cache.tags.tagsinuse 13749.059276 # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs 10995274 # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs 3202540 # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs 3.433298 # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle 10289671385000 # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 3719.678025 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 60.787845 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 70.255948 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 738.115958 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2404.101650 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6756.119849 # Average occupied blocks per requestor
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+system.cpu1.l2cache.tags.occ_percent::total 0.839176 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9826 # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023 113 # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6274 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 142 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 1008 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2026 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4347 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 2303 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 5 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 31 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 61 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 496 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1278 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3095 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1333 # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.599731 # Percentage of cache occupancy per task id
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+system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.382935 # Percentage of cache occupancy per task id
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+system.cpu1.l2cache.ReadReq_hits::total 8017061 # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks 3078590 # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total 3078590 # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 84508 # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total 84508 # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 36910 # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total 36910 # number of SCUpgradeReq hits
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+system.cpu1.l2cache.overall_hits::cpu1.inst 4837723 # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data 3754383 # number of overall hits
+system.cpu1.l2cache.overall_hits::total 8959850 # number of overall hits
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+system.cpu1.l2cache.ReadReq_misses::cpu1.inst 181059 # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.data 1016624 # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total 1222158 # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 110012 # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total 110012 # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 159084 # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total 159084 # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 8 # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data 227840 # number of ReadExReq misses
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+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 55683.057689 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21007.174994 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 25744.677294 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25571.323344 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29486.100365 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 29486.100365 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17259.392339 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17259.392339 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13963.073546 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13963.073546 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 229562.500000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 229562.500000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36178.155824 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36178.155824 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38969.985947 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 55683.057689 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21007.174994 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27614.347108 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27233.457341 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38969.985947 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 55683.057689 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21007.174994 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27614.347108 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29486.100365 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28674.608848 # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dcache.tags.replacements 5412769 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 455.628997 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 156797756 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 5413278 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 28.965399 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 8374220312000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.628997 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.889900 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.889900 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 330228848 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 330228848 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 79329783 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 79329783 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 73242746 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 73242746 # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data 190572 # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total 190572 # number of SoftPFReq hits
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+system.cpu1.dcache.WriteInvalidateReq_hits::total 704958 # number of WriteInvalidateReq hits
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+system.cpu1.dcache.LoadLockedReq_hits::total 1728485 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1710118 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 1710118 # number of StoreCondReq hits
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+system.cpu1.dcache.overall_hits::total 152763101 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 3054941 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 3054941 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 1365411 # number of WriteReq misses
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+system.cpu1.dcache.SoftPFReq_misses::total 663261 # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 178994 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 178994 # number of LoadLockedReq misses
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+system.cpu1.dcache.StoreCondReq_misses::total 196091 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 4420352 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 4420352 # number of demand (read+write) misses
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+system.cpu1.dcache.overall_misses::total 5083613 # number of overall misses
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+system.cpu1.dcache.ReadReq_miss_latency::total 45633904603 # number of ReadReq miss cycles
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+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2574333319 # number of LoadLockedReq miss cycles
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+system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2386500 # number of StoreCondFailReq miss cycles
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+system.cpu1.dcache.ReadReq_accesses::total 82384724 # number of ReadReq accesses(hits+misses)
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+system.cpu1.dcache.SoftPFReq_accesses::total 853833 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 704958 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::total 704958 # number of WriteInvalidateReq accesses(hits+misses)
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+system.cpu1.dcache.LoadLockedReq_accesses::total 1907479 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu1.dcache.overall_accesses::total 157846714 # number of overall (read+write) accesses
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+system.cpu1.dcache.ReadReq_miss_rate::total 0.037081 # miss rate for ReadReq accesses
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+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.776804 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.093838 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.093838 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102870 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102870 # miss rate for StoreCondReq accesses
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+system.cpu1.dcache.demand_miss_rate::total 0.028156 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032206 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.032206 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14937.736802 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14937.736802 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17029.266427 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 17029.266427 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14382.232471 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14382.232471 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21185.294715 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21185.294715 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15583.793396 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 15583.793396 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13550.569704 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 13550.569704 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes 704958 # number of fast writes performed
+system.cpu1.dcache.cache_copies 0 # number of cache copies performed
+system.cpu1.dcache.writebacks::writebacks 3078594 # number of writebacks
+system.cpu1.dcache.writebacks::total 3078594 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 23839 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 23839 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 436 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 436 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45139 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45139 # number of LoadLockedReq MSHR hits
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+system.cpu1.dcache.demand_mshr_hits::total 24275 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 24275 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 24275 # number of overall MSHR hits
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+system.cpu1.dcache.ReadReq_mshr_misses::total 3031102 # number of ReadReq MSHR misses
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+system.cpu1.dcache.SoftPFReq_mshr_misses::total 663261 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 133855 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 133855 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 196002 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 196002 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 4396077 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 4396077 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 5059338 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 5059338 # number of overall MSHR misses
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+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38375786357 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20437608309 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20437608309 # number of WriteReq MSHR miss cycles
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+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14184435008 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 31455228300 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 31455228300 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1522508206 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1522508206 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3750879374 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3750879374 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2276500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2276500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 58813394666 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 58813394666 # number of demand (read+write) MSHR miss cycles
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+system.cpu1.dcache.overall_mshr_miss_latency::total 72997829674 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3974280487 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3974280487 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3786981721 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3786981721 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7761262208 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7761262208 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036792 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036792 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018295 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018295 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.776804 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.776804 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.070174 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.070174 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.102823 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.102823 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028002 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.028002 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032052 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.032052 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12660.671385 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12660.671385 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14972.881048 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14972.881048 # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21385.902394 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21385.902394 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11374.309559 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11374.309559 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19136.944388 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19136.944388 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13378.608852 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13378.608852 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14428.336212 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14428.336212 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.toL2Bus.trans_dist::ReadReq 12531191 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 9460246 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 22034 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 22034 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 3078590 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 3649719 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1670210 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 704958 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 365743 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350744 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 452026 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1320531 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1177447 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 10037784 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15516501 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332477 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 559655 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 26446417 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 321202488 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 568398888 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1205080 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1932672 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 892739128 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 8517318 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 22943145 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 5.359651 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.479898 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5 14691626 64.03% 64.03% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6 8251519 35.97% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 22943145 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 11163844442 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 175587993 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer0.occupancy 7529809391 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer1.occupancy 8141370258 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer2.occupancy 182479297 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer3.occupancy 318532791 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.replacements 115665 # number of replacements
+system.iocache.tags.tagsinuse 11.304646 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115681 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 9130394779000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 7.406620 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 3.898026 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.462914 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.243627 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.706540 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 1041810 # Number of tag accesses
+system.iocache.tags.data_accesses 1041810 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 106728 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 106728 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8941 # number of ReadReq misses
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+system.iocache.overall_misses::realview.ide 8941 # number of overall misses
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+system.iocache.ReadReq_miss_latency::realview.ide 1994628595 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 2000335595 # number of ReadReq miss cycles
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+system.iocache.ReadReq_accesses::realview.ide 8941 # number of ReadReq accesses(hits+misses)
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+system.iocache.overall_accesses::total 8981 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
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+system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
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+system.iocache.ReadReq_avg_miss_latency::realview.ide 223087.864333 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 222804.142905 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency
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+system.iocache.demand_avg_miss_latency::realview.ide 223087.864333 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 222769.468322 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 223087.864333 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 222769.468322 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 55195 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.053734 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 106728 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide 8941 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 8978 # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
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+system.iocache.demand_mshr_misses::realview.ide 8941 # number of demand (read+write) MSHR misses
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+system.iocache.ReadReq_mshr_miss_latency::total 1533322613 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6584739086 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6584739086 # number of WriteInvalidateReq MSHR miss cycles
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+system.iocache.demand_mshr_miss_latency::realview.ide 1529539613 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 1533523613 # number of demand (read+write) MSHR miss cycles
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+system.iocache.overall_mshr_miss_latency::realview.ide 1529539613 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 1533523613 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 171070.306789 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 170786.657719 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 171070.306789 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 170751.988977 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 171070.306789 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 170751.988977 # average overall mshr miss latency
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
+atags_addr=134217728
+boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
+eventq_index=0
+flags_addr=469827632
+gic_cpu_addr=738205696
+have_generic_timer=false
+have_large_asid_64=false
+have_lpae=false
+have_security=false
+have_virtualization=false
+highest_el_is_64=false
+init_param=0
+kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel_addr_check=true
+load_addr_mask=268435455
+load_offset=2147483648
+machine_type=VExpress_EMM64
+mem_mode=timing
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.vram system.realview.nvmem
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+phys_addr_range_64=40
+readfile=/work/gem5.latest/tests/halt.sh
+reset_addr_64=0
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.bridge]
+type=Bridge
+clk_domain=system.clk_domain
+delay=50000
+eventq_index=0
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+eventq_index=0
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+eventq_index=0
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+eventq_index=0
+image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
+dtb=system.cpu.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+workload=
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+tlb=system.cpu.dtb
+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[5]
+
+[system.cpu.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[3]
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=1
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[4]
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+use_default_range=true
+width=8
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
+eventq_index=0
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=2147483648:2415919103
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
+tWTR=7500
+tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 16:01:52
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu.isa: ISA system set to: 0x500ab00 0x500ab00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80080000
+info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 51781056074000 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 51.781056 # Number of seconds simulated
+sim_ticks 51781056074000 # Number of ticks simulated
+final_tick 51781056074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 717486 # Simulator instruction rate (inst/s)
+host_op_rate 843154 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44175728553 # Simulator tick rate (ticks/s)
+host_mem_usage 650840 # Number of bytes of host memory used
+host_seconds 1172.16 # Real time elapsed on the host
+sim_insts 841009423 # Number of instructions simulated
+sim_ops 988312418 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::realview.ide 385216 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 437760 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 790272 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 4324596 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 53060296 # Number of bytes read from this memory
+system.physmem.bytes_read::total 58998140 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 4324596 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 4324596 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 30687936 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 99485540 # Number of bytes written to this memory
+system.physmem.bytes_written::total 136999972 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 6019 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 6840 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 12348 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 107979 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 829080 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 962266 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 479499 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data 1556713 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 2142876 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 7439 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 8454 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 15262 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 83517 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1024705 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1139377 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 83517 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 83517 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 592648 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 131834 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1921273 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2645755 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 592648 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 139273 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 8454 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 15262 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 83517 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2945978 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3785132 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 962266 # Number of read requests accepted
+system.physmem.writeReqs 2142876 # Number of write requests accepted
+system.physmem.readBursts 962266 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 2142876 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 61369728 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 215296 # Total number of bytes read from write queue
+system.physmem.bytesWritten 132432768 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 58998140 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 136999972 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 3364 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 73592 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 33443 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 65026 # Per bank write bursts
+system.physmem.perBankRdBursts::1 59757 # Per bank write bursts
+system.physmem.perBankRdBursts::2 57697 # Per bank write bursts
+system.physmem.perBankRdBursts::3 55201 # Per bank write bursts
+system.physmem.perBankRdBursts::4 59686 # Per bank write bursts
+system.physmem.perBankRdBursts::5 66424 # Per bank write bursts
+system.physmem.perBankRdBursts::6 54909 # Per bank write bursts
+system.physmem.perBankRdBursts::7 46752 # Per bank write bursts
+system.physmem.perBankRdBursts::8 56185 # Per bank write bursts
+system.physmem.perBankRdBursts::9 105428 # Per bank write bursts
+system.physmem.perBankRdBursts::10 56738 # Per bank write bursts
+system.physmem.perBankRdBursts::11 56925 # Per bank write bursts
+system.physmem.perBankRdBursts::12 52656 # Per bank write bursts
+system.physmem.perBankRdBursts::13 52461 # Per bank write bursts
+system.physmem.perBankRdBursts::14 54958 # Per bank write bursts
+system.physmem.perBankRdBursts::15 58099 # Per bank write bursts
+system.physmem.perBankWrBursts::0 127089 # Per bank write bursts
+system.physmem.perBankWrBursts::1 113639 # Per bank write bursts
+system.physmem.perBankWrBursts::2 227284 # Per bank write bursts
+system.physmem.perBankWrBursts::3 120346 # Per bank write bursts
+system.physmem.perBankWrBursts::4 128596 # Per bank write bursts
+system.physmem.perBankWrBursts::5 124885 # Per bank write bursts
+system.physmem.perBankWrBursts::6 105979 # Per bank write bursts
+system.physmem.perBankWrBursts::7 88244 # Per bank write bursts
+system.physmem.perBankWrBursts::8 113178 # Per bank write bursts
+system.physmem.perBankWrBursts::9 146103 # Per bank write bursts
+system.physmem.perBankWrBursts::10 105873 # Per bank write bursts
+system.physmem.perBankWrBursts::11 119118 # Per bank write bursts
+system.physmem.perBankWrBursts::12 106014 # Per bank write bursts
+system.physmem.perBankWrBursts::13 144894 # Per bank write bursts
+system.physmem.perBankWrBursts::14 168059 # Per bank write bursts
+system.physmem.perBankWrBursts::15 129961 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 15 # Number of times write queue was full causing retry
+system.physmem.totGap 51781053518000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 43101 # Read request sizes (log2)
+system.physmem.readPktSize::3 13 # Read request sizes (log2)
+system.physmem.readPktSize::4 2 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 919150 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 1 # Write request sizes (log2)
+system.physmem.writePktSize::3 2572 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 2140303 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 916619 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 36737 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 2160 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 554 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 703 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 360 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 332 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 262 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 188 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 124 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 116 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 110 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 103 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 99 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 93 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 91 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 80 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 78 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 50 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 40 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 84352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 107983 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 131098 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::19 123261 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::22 132602 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 122703 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 125765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 114111 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::35 1714 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 1256 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 957 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 643 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 439 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 337 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 303 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 280 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 299 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 327 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 302 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 285 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 261 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 233 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 208 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 161 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 140 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 123 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 107 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 97 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 80 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 65 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 65 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 55 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 43 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 577071 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 335.837219 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 186.071808 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 364.354794 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 225600 39.09% 39.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 129681 22.47% 61.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 48337 8.38% 69.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 25344 4.39% 74.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 16032 2.78% 77.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 12773 2.21% 79.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 9903 1.72% 81.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 10527 1.82% 82.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 98874 17.13% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 577071 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 103651 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 9.251131 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 174.136795 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 103646 100.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-6143 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::20480-22527 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::22528-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::43008-45055 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 103651 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 103651 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.963744 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 19.612401 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 5.068688 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 47209 45.55% 45.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 51400 49.59% 95.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 1703 1.64% 96.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 1371 1.32% 98.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 882 0.85% 98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 145 0.14% 99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 167 0.16% 99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 75 0.07% 99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 86 0.08% 99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 15 0.01% 99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 11 0.01% 99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 14 0.01% 99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 393 0.38% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 31 0.03% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 40 0.04% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 32 0.03% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 31 0.03% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 1 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 1 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 13 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 1 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 17 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 3 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 2 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 103651 # Writes before turning the bus around for reads
+system.physmem.totQLat 10497513500 # Total ticks spent queuing
+system.physmem.totMemAccLat 28476926000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 4794510000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10947.43 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 29697.43 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.19 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.56 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.65 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing
+system.physmem.readRowHits 723659 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1727431 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 75.47 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 83.48 # Row buffer hit rate for writes
+system.physmem.avgGap 16675905.17 # Average gap between requests
+system.physmem.pageHitRate 80.94 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 49473510377000 # Time in different power states
+system.physmem.memoryStateTime::REF 1729083200000 # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem.memoryStateTime::ACT 578461163500 # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem.actEnergy::0 2226745080 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 2135911680 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 1214989875 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 1165428000 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 3630494400 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 3848871000 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 6713681760 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 6695136000 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 3382086739200 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 3382086739200 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 1381227557085 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 1374892031880 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 29857029495750 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 29862586974000 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 34634129703150 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 34633411091760 # Total energy per rank (pJ)
+system.physmem.averagePower::0 668.857174 # Core power per rank (mW)
+system.physmem.averagePower::1 668.843296 # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 445419 # Transaction distribution
+system.membus.trans_dist::ReadResp 445419 # Transaction distribution
+system.membus.trans_dist::WriteReq 33871 # Transaction distribution
+system.membus.trans_dist::WriteResp 33871 # Transaction distribution
+system.membus.trans_dist::Writeback 479499 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 1660804 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 1660804 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 33447 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 33449 # Transaction distribution
+system.membus.trans_dist::ReadExReq 553497 # Transaction distribution
+system.membus.trans_dist::ReadExResp 553497 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6936 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5572311 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5702495 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 228222 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 228222 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5930717 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13872 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 188786400 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 188956724 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7211712 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7211712 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 196168436 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 2862 # Total snoops (count)
+system.membus.snoop_fanout::samples 3095773 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3095773 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 3095773 # Request fanout histogram
+system.membus.reqLayer0.occupancy 106099500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 5682499 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 21134514240 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 11065598028 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer3.occupancy 186599963 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
+system.iobus.trans_dist::ReadReq 40401 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40401 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136730 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136733 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 3 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230998 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230998 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 354268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334424 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334424 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7492830 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 981107027 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 179038037 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 158219223 # DTB read hits
+system.cpu.dtb.read_misses 140465 # DTB read misses
+system.cpu.dtb.write_hits 143634632 # DTB write hits
+system.cpu.dtb.write_misses 49220 # DTB write misses
+system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 38918 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 71391 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 7071 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 18891 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 158359688 # DTB read accesses
+system.cpu.dtb.write_accesses 143683852 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 301853855 # DTB hits
+system.cpu.dtb.misses 189685 # DTB misses
+system.cpu.dtb.accesses 302043540 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 841528845 # ITB inst hits
+system.cpu.itb.inst_misses 119634 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 38918 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 51154 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 841648479 # ITB inst accesses
+system.cpu.itb.hits 841528845 # DTB hits
+system.cpu.itb.misses 119634 # DTB misses
+system.cpu.itb.accesses 841648479 # DTB accesses
+system.cpu.numCycles 103562112148 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 841009423 # Number of instructions committed
+system.cpu.committedOps 988312418 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 908272324 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 899019 # Number of float alu accesses
+system.cpu.num_func_calls 50313277 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 127741607 # number of instructions that are conditional controls
+system.cpu.num_int_insts 908272324 # number of integer instructions
+system.cpu.num_fp_insts 899019 # number of float instructions
+system.cpu.num_int_register_reads 1317064952 # number of times the integer registers were read
+system.cpu.num_int_register_writes 720072212 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 1450897 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 759632 # number of times the floating registers were written
+system.cpu.num_cc_register_reads 218662872 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 218058310 # number of times the CC registers were written
+system.cpu.num_mem_refs 301832909 # number of memory refs
+system.cpu.num_load_insts 158209551 # Number of load instructions
+system.cpu.num_store_insts 143623358 # Number of store instructions
+system.cpu.num_idle_cycles 100527171614.894058 # Number of idle cycles
+system.cpu.num_busy_cycles 3034940533.105942 # Number of busy cycles
+system.cpu.not_idle_fraction 0.029306 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.970694 # Percentage of idle cycles
+system.cpu.Branches 187669847 # Number of branches fetched
+system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 684692132 69.24% 69.24% # Class of executed instruction
+system.cpu.op_class::IntMult 2140683 0.22% 69.46% # Class of executed instruction
+system.cpu.op_class::IntDiv 96951 0.01% 69.47% # Class of executed instruction
+system.cpu.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 8 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 13 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 21 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 112246 0.01% 69.48% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 69.48% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.48% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.48% # Class of executed instruction
+system.cpu.op_class::MemRead 158209551 16.00% 85.48% # Class of executed instruction
+system.cpu.op_class::MemWrite 143623358 14.52% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 988874964 # Class of executed instruction
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.quiesce 16062 # number of quiesce instructions executed
+system.cpu.icache.tags.replacements 13492469 # number of replacements
+system.cpu.icache.tags.tagsinuse 511.894753 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 828035859 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 13492981 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 61.367896 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 31319075250 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 511.894753 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.999794 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.999794 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 855021831 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 855021831 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 828035859 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 828035859 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 828035859 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 828035859 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 828035859 # number of overall hits
+system.cpu.icache.overall_hits::total 828035859 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 13492986 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 13492986 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 13492986 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 13492986 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 13492986 # number of overall misses
+system.cpu.icache.overall_misses::total 13492986 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 179568208714 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 179568208714 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 179568208714 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 179568208714 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 179568208714 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 179568208714 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 841528845 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 841528845 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 841528845 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 841528845 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 841528845 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 841528845 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016034 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.016034 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.016034 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.016034 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.016034 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.016034 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13308.263176 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13308.263176 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13308.263176 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13308.263176 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13308.263176 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13308.263176 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13492986 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 13492986 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 13492986 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 13492986 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 13492986 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 13492986 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 152559106286 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 152559106286 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 152559106286 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 152559106286 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 152559106286 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 152559106286 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2831639000 # number of ReadReq MSHR uncacheable cycles
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004808 # mshr miss rate for overall accesses
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+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
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+system.cpu.dcache.tags.avg_refs 30.940226 # Average number of references to valid blocks.
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+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 1554140 # number of fast writes performed
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+system.cpu.dcache.writebacks::total 6407423 # number of writebacks
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13596.981960 # average ReadReq mshr miss latency
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+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15110.546163 # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data inf # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12012.414680 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12012.414680 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17820.110737 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17820.110737 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17431.861393 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17431.861393 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 20761818 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 20753624 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 33871 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 33871 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 6407423 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1660819 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1554140 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 42524 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 42526 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1952681 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1952681 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27072222 # Packet count per connected master and slave (bytes)
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+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601299 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 874780 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 54730977 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 863723604 # Cumulative packet size per connected master and slave (bytes)
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+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1950336 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2556184 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 1904274380 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 465684 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 30748357 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5.003758 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.061188 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 30632803 99.62% 99.62% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 115554 0.38% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 30748357 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 23350352499 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy 1018500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 20304235714 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 13344056707 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy 358207000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy 555725500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.replacements 115481 # number of replacements
+system.iocache.tags.tagsinuse 10.454792 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115497 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 13153677258000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.509713 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.945079 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.219357 # Average percentage of cache occupancy
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+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 1039872 # Number of tag accesses
+system.iocache.tags.data_accesses 1039872 # Number of data accesses
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+system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits
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+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
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+system.iocache.ReadReq_avg_miss_latency::realview.ide 214902.248104 # average ReadReq miss latency
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+system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency
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+system.iocache.demand_avg_miss_latency::total 214589.899944 # average overall miss latency
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+system.iocache.overall_avg_miss_latency::realview.ide 214902.248104 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 214589.899944 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 51753 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 106664 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
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+system.iocache.ReadReq_mshr_misses::realview.ide 8835 # number of ReadReq MSHR misses
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+system.iocache.demand_mshr_miss_latency::realview.ide 1439157862 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 1442901862 # number of demand (read+write) MSHR miss cycles
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+system.iocache.overall_mshr_miss_latency::realview.ide 1439157862 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 1442901862 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
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+system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 162892.797057 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 162614.840171 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 162892.797057 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 162580.491493 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 162892.797057 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 162580.491493 # average overall mshr miss latency
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
+atags_addr=134217728
+boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
+eventq_index=0
+flags_addr=469827632
+gic_cpu_addr=738205696
+have_generic_timer=false
+have_large_asid_64=false
+have_lpae=false
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+have_virtualization=false
+highest_el_is_64=false
+init_param=0
+kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel_addr_check=true
+load_addr_mask=268435455
+load_offset=2147483648
+machine_type=VExpress_EMM64
+mem_mode=atomic
+mem_ranges=2147483648:2415919103
+memories=system.realview.nvmem system.physmem system.realview.vram
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+phys_addr_range_64=40
+readfile=/work/gem5.latest/tests/halt.sh
+reset_addr_64=0
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.bridge]
+type=Bridge
+clk_domain=system.clk_domain
+delay=50000
+eventq_index=0
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+eventq_index=0
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+eventq_index=0
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+eventq_index=0
+image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu0]
+type=AtomicSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu0.dstage2_mmu
+dtb=system.cpu0.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+istage2_mmu=system.cpu0.istage2_mmu
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+width=1
+workload=
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu0.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+tlb=system.cpu0.dtb
+
+[system.cpu0.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu0.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[5]
+
+[system.cpu0.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[3]
+
+[system.cpu0.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=1
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu0.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu0.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu0.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+tlb=system.cpu0.itb
+
+[system.cpu0.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu0.istage2_mmu.stage2_tlb.walker
+
+[system.cpu0.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[4]
+
+[system.cpu0.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu0.itb.walker
+
+[system.cpu0.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[2]
+
+[system.cpu0.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu1]
+type=AtomicSimpleCPU
+children=dstage2_mmu dtb isa istage2_mmu itb tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu1.dstage2_mmu
+dtb=system.cpu1.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=Null
+isa=system.cpu1.isa
+istage2_mmu=system.cpu1.istage2_mmu
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=true
+system=system
+tracer=system.cpu1.tracer
+width=1
+workload=
+
+[system.cpu1.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+tlb=system.cpu1.dtb
+
+[system.cpu1.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu1.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu1.dtb.walker
+
+[system.cpu1.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu1.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+tlb=system.cpu1.itb
+
+[system.cpu1.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu1.istage2_mmu.stage2_tlb.walker
+
+[system.cpu1.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+use_default_range=true
+width=8
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
+eventq_index=0
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.l2c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.l2c.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2415919103
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 16:13:02
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+ 0: system.cpu0.isa: ISA system set to: 0x5318b00 0x5318b00
+ 0: system.cpu1.isa: ISA system set to: 0x5318b00 0x5318b00
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 51.111167 # Number of seconds simulated
+sim_ticks 51111167186000 # Number of ticks simulated
+final_tick 51111167186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1245007 # Simulator instruction rate (inst/s)
+host_op_rate 1463153 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 64786832406 # Simulator tick rate (ticks/s)
+host_mem_usage 666372 # Number of bytes of host memory used
+host_seconds 788.91 # Real time elapsed on the host
+sim_insts 982202425 # Number of instructions simulated
+sim_ops 1154300154 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.ide 441600 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 336512 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 497152 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 3037748 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 46051464 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 337024 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 478912 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 2057984 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 44726784 # Number of bytes read from this memory
+system.physmem.bytes_read::total 97965180 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 3037748 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 2057984 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5095732 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 65987776 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 57990628 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 43345472 # Number of bytes written to this memory
+system.physmem.bytes_written::total 174150372 # Number of bytes written to this memory
+system.physmem.num_reads::realview.ide 6900 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 5258 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 7768 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 87872 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 719567 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 5266 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 7483 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 32156 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 698856 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1571126 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1031059 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 908355 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 677273 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 2723351 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.ide 8640 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 6584 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 9727 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 59434 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 901006 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 6594 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 9370 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 40265 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 875088 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1916708 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 59434 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 40265 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 99699 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1291064 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 133562 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 1134598 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 848063 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3407286 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1291064 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 142202 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 6584 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 9727 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 59434 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 2035604 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 6594 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 9370 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 40265 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 1723151 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 5323994 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 581619 # Transaction distribution
+system.membus.trans_dist::ReadResp 581619 # Transaction distribution
+system.membus.trans_dist::WriteReq 33712 # Transaction distribution
+system.membus.trans_dist::WriteResp 33712 # Transaction distribution
+system.membus.trans_dist::Writeback 1031059 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 1689719 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 1689719 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 40044 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 40045 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1025076 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1025076 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122798 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 7410857 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 7540367 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 231034 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 231034 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 7771401 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155928 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 264847648 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 265017016 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7392896 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7392896 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 272409912 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 4290786 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 4290786 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 4290786 # Request fanout histogram
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.l2c.tags.replacements 1249718 # number of replacements
+system.l2c.tags.tagsinuse 64613.042702 # Cycle average of tags in use
+system.l2c.tags.total_refs 29438941 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 1311508 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 22.446635 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 13800320247500 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 36057.882399 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker 161.314219 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker 260.482704 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 3661.102067 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 9854.563004 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker 162.816685 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker 224.976066 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 2766.895079 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 11463.010480 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.550200 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002461 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker 0.003975 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst 0.055864 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.150369 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002484 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker 0.003433 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.042219 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data 0.174912 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.985917 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023 446 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024 61344 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4 435 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 2192 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3 4810 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4 53981 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023 0.006805 # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024 0.936035 # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses 284052655 # Number of tag accesses
+system.l2c.tags.data_accesses 284052655 # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker 278747 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 141162 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst 7094152 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 3728500 # number of ReadReq hits
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+system.l2c.ReadReq_hits::cpu1.itb.walker 137718 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 7094701 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 3721109 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 22471572 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 7859784 # number of Writeback hits
+system.l2c.Writeback_hits::total 7859784 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 6010 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 5720 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 11730 # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 752229 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 739129 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 1491358 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker 278747 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker 141162 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 7094152 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 4480729 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker 275483 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker 137718 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 7094701 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 4460238 # number of demand (read+write) hits
+system.l2c.demand_hits::total 23962930 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker 278747 # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker 141162 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 7094152 # number of overall hits
+system.l2c.overall_hits::cpu0.data 4480729 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 275483 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 137718 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 7094701 # number of overall hits
+system.l2c.overall_hits::cpu1.data 4460238 # number of overall hits
+system.l2c.overall_hits::total 23962930 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker 5258 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker 7768 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst 44771 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 202781 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker 5266 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker 7483 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 32156 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 190554 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 496037 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 20061 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 19420 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 39481 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 517033 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 508603 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 1025636 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker 5258 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker 7768 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 44771 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 719814 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker 5266 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker 7483 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 32156 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 699157 # number of demand (read+write) misses
+system.l2c.demand_misses::total 1521673 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker 5258 # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker 7768 # number of overall misses
+system.l2c.overall_misses::cpu0.inst 44771 # number of overall misses
+system.l2c.overall_misses::cpu0.data 719814 # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker 5266 # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker 7483 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 32156 # number of overall misses
+system.l2c.overall_misses::cpu1.data 699157 # number of overall misses
+system.l2c.overall_misses::total 1521673 # number of overall misses
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 284005 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 148930 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 7138923 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 3931281 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 280749 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 145201 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 7126857 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 3911663 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 22967609 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 7859784 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 7859784 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 26071 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 25140 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 51211 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 1269262 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 1247732 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 2516994 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 284005 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 148930 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 7138923 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 5200543 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 280749 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 145201 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 7126857 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 5159395 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 25484603 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 284005 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 148930 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 7138923 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 5200543 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 280749 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 145201 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 7126857 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 5159395 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 25484603 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.018514 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.052159 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.006271 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.051581 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.018757 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.051535 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.004512 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.048714 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.021597 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.769476 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.772474 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.770948 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.407349 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.407622 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.407484 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.018514 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.052159 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.006271 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.138411 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.018757 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker 0.051535 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.004512 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.135511 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.059710 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.018514 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.052159 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.006271 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.138411 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.018757 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker 0.051535 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.004512 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.135511 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.059710 # miss rate for overall accesses
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.writebacks::writebacks 1031059 # number of writebacks
+system.l2c.writebacks::total 1031059 # number of writebacks
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
+system.toL2Bus.trans_dist::ReadReq 23429115 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 23429115 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 33712 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 33712 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 7859784 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 1583055 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 1583055 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 51211 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 51212 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 2516994 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 2516994 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28617810 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31982832 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 830190 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1657128 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 63087960 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 913182420 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1267567716 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3320760 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6628512 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 2190699408 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 116124 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 35478945 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 5.003256 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.056968 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 35363428 99.67% 99.67% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 115517 0.33% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 35478945 # Request fanout histogram
+system.iobus.trans_dist::ReadReq 40295 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40295 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136621 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29957 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47916 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122798 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353832 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47936 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155928 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7492262 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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+system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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+system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 91814340 # DTB read hits
+system.cpu0.dtb.read_misses 108240 # DTB read misses
+system.cpu0.dtb.write_hits 84018556 # DTB write hits
+system.cpu0.dtb.write_misses 37258 # DTB write misses
+system.cpu0.dtb.flush_tlb 51122 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 25424 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 574 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 56720 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 4774 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 10954 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 91922580 # DTB read accesses
+system.cpu0.dtb.write_accesses 84055814 # DTB write accesses
+system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dtb.hits 175832896 # DTB hits
+system.cpu0.dtb.misses 145498 # DTB misses
+system.cpu0.dtb.accesses 175978394 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.inst_hits 492376635 # ITB inst hits
+system.cpu0.itb.inst_misses 70812 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.flush_tlb 51122 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 25424 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 574 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 40507 # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.inst_accesses 492447447 # ITB inst accesses
+system.cpu0.itb.hits 492376635 # DTB hits
+system.cpu0.itb.misses 70812 # DTB misses
+system.cpu0.itb.accesses 492447447 # DTB accesses
+system.cpu0.numCycles 98037034508 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.committedInsts 492157902 # Number of instructions committed
+system.cpu0.committedOps 578109926 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 529630902 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 450855 # Number of float alu accesses
+system.cpu0.num_func_calls 28493711 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 76041471 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 529630902 # number of integer instructions
+system.cpu0.num_fp_insts 450855 # number of float instructions
+system.cpu0.num_int_register_reads 782881083 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 420743584 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 732582 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 369632 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 132702849 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 132381135 # number of times the CC registers were written
+system.cpu0.num_mem_refs 175956600 # number of memory refs
+system.cpu0.num_load_insts 91908955 # Number of load instructions
+system.cpu0.num_store_insts 84047645 # Number of store instructions
+system.cpu0.num_idle_cycles 96929537952.996140 # Number of idle cycles
+system.cpu0.num_busy_cycles 1107496555.003859 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.011297 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.988703 # Percentage of idle cycles
+system.cpu0.Branches 110099418 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 401202102 69.36% 69.36% # Class of executed instruction
+system.cpu0.op_class::IntMult 1174212 0.20% 69.56% # Class of executed instruction
+system.cpu0.op_class::IntDiv 49936 0.01% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 53534 0.01% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::MemRead 91908955 15.89% 85.47% # Class of executed instruction
+system.cpu0.op_class::MemWrite 84047645 14.53% 100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu0.op_class::total 578436384 # Class of executed instruction
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 16775 # number of quiesce instructions executed
+system.cpu0.icache.tags.replacements 14265263 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 968528346 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 14265775 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 67.891744 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 268.596875 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 243.387725 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.524603 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst 0.475367 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses 997059906 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 997059906 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 485302312 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 483226034 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 968528346 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 485302312 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst 483226034 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 968528346 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 485302312 # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst 483226034 # number of overall hits
+system.cpu0.icache.overall_hits::total 968528346 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 7138923 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst 7126857 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 14265780 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 7138923 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst 7126857 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 14265780 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 7138923 # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst 7126857 # number of overall misses
+system.cpu0.icache.overall_misses::total 14265780 # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 492441235 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst 490352891 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 982794126 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 492441235 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst 490352891 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 982794126 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 492441235 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst 490352891 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 982794126 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014497 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014534 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014497 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014534 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.014516 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014497 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014534 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.014516 # miss rate for overall accesses
+system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.dcache.tags.replacements 11606183 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 339855525 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 11606695 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 29.280990 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 263.642084 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data 248.357636 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.514926 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data 0.485074 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses 1417455640 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 1417455640 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 85601256 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data 85509652 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 171110908 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 79544795 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data 79528789 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 159073584 # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209342 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data 214988 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 424330 # number of SoftPFReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 905782 # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 677273 # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::total 1583055 # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2149143 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 2154415 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 4303558 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2275069 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2280579 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 4555648 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 165146051 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data 165038441 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 330184492 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 165355393 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data 165253429 # number of overall hits
+system.cpu0.dcache.overall_hits::total 330608822 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 3016346 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data 2986822 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 6003168 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1295333 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data 1272872 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 2568205 # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 788110 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data 797772 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total 1585882 # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 126825 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 127069 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 253894 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 4311679 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data 4259694 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 8571373 # number of demand (read+write) misses
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+system.cpu0.dcache.overall_misses::cpu1.data 5057466 # number of overall misses
+system.cpu0.dcache.overall_misses::total 10157255 # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 88617602 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data 88496474 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 177114076 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 80840128 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data 80801661 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 161641789 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 997452 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 1012760 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total 2010212 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 905782 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 677273 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::total 1583055 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2275968 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2281484 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 4557452 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2275069 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2280580 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 4555649 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 169457730 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data 169298135 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 338755865 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 170455182 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data 170310895 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 340766077 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.034038 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033751 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.033894 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016023 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015753 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.790123 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.787721 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788913 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055724 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.055696 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055710 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000000 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025444 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025161 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.025303 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029919 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029695 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.029807 # miss rate for overall accesses
+system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes 1583055 # number of fast writes performed
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks 7859784 # number of writebacks
+system.cpu0.dcache.writebacks::total 7859784 # number of writebacks
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.inst_hits 0 # ITB inst hits
+system.cpu1.dtb.inst_misses 0 # ITB inst misses
+system.cpu1.dtb.read_hits 91711295 # DTB read hits
+system.cpu1.dtb.read_misses 106129 # DTB read misses
+system.cpu1.dtb.write_hits 83753398 # DTB write hits
+system.cpu1.dtb.write_misses 37024 # DTB write misses
+system.cpu1.dtb.flush_tlb 51111 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 24347 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 565 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 56316 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 4760 # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults 10697 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 91817424 # DTB read accesses
+system.cpu1.dtb.write_accesses 83790422 # DTB write accesses
+system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dtb.hits 175464693 # DTB hits
+system.cpu1.dtb.misses 143153 # DTB misses
+system.cpu1.dtb.accesses 175607846 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.inst_hits 490289476 # ITB inst hits
+system.cpu1.itb.inst_misses 69341 # ITB inst misses
+system.cpu1.itb.read_hits 0 # DTB read hits
+system.cpu1.itb.read_misses 0 # DTB read misses
+system.cpu1.itb.write_hits 0 # DTB write hits
+system.cpu1.itb.write_misses 0 # DTB write misses
+system.cpu1.itb.flush_tlb 51111 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 24347 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 565 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 40524 # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses 0 # DTB read accesses
+system.cpu1.itb.write_accesses 0 # DTB write accesses
+system.cpu1.itb.inst_accesses 490358817 # ITB inst accesses
+system.cpu1.itb.hits 490289476 # DTB hits
+system.cpu1.itb.misses 69341 # DTB misses
+system.cpu1.itb.accesses 490358817 # DTB accesses
+system.cpu1.numCycles 97462079825 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.committedInsts 490044523 # Number of instructions committed
+system.cpu1.committedOps 576190228 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 528250346 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 430494 # Number of float alu accesses
+system.cpu1.num_func_calls 28340448 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 75582064 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 528250346 # number of integer instructions
+system.cpu1.num_fp_insts 430494 # number of float instructions
+system.cpu1.num_int_register_reads 777877517 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 419772646 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 687185 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 378928 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 131315601 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 131059540 # number of times the CC registers were written
+system.cpu1.num_mem_refs 175582943 # number of memory refs
+system.cpu1.num_load_insts 91803462 # Number of load instructions
+system.cpu1.num_store_insts 83779481 # Number of store instructions
+system.cpu1.num_idle_cycles 96357524268.359177 # Number of idle cycles
+system.cpu1.num_busy_cycles 1104555556.640824 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.011333 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.988667 # Percentage of idle cycles
+system.cpu1.Branches 109434059 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 399630543 69.32% 69.32% # Class of executed instruction
+system.cpu1.op_class::IntMult 1180172 0.20% 69.53% # Class of executed instruction
+system.cpu1.op_class::IntDiv 50607 0.01% 69.53% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 54288 0.01% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::MemRead 91803462 15.92% 85.47% # Class of executed instruction
+system.cpu1.op_class::MemWrite 83779481 14.53% 100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::total 576498596 # Class of executed instruction
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.iocache.tags.replacements 115459 # number of replacements
+system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 1039650 # Number of tag accesses
+system.iocache.tags.data_accesses 1039650 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses
+system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
+system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
+system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8853 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
+system.iocache.overall_misses::realview.ide 8813 # number of overall misses
+system.iocache.overall_misses::total 8853 # number of overall misses
+system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 106664 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff