Revert "Vivado does not like zero width port connections"

This reverts commit 895e2befa76bd326cc47fd40de112ea067fcaf98.

diff --git a/techlibs/xilinx/xilinx_finalise.cc b/techlibs/xilinx/xilinx_finalise.cc
index 2c0bd3534b4bb7cf2581f73e5d27e6b0393fac90..db73babe315ce64c4043c1c5c5acb10b3d308a73 100644 (file)
--- a/techlibs/xilinx/xilinx_finalise.cc
+++ b/techlibs/xilinx/xilinx_finalise.cc
@@ -53,7 +53,7 @@ struct XilinxFinalisePass : public Pass
                for (auto cell : module->selected_cells()) {
                        if (cell->type != ID(DSP48E1))
                                continue;
-                       for (auto conn : cell->connections()) {
+                       for (auto &conn : cell->connections_) {
                                if (!cell->output(conn.first))
                                        continue;
                                bool purge = true;
@@ -74,7 +74,7 @@ struct XilinxFinalisePass : public Pass
 
                                if (purge) {
                                        log_debug("Purging unused port connection %s %s (.%s(%s))\n", cell->type.c_str(), log_id(cell), log_id(conn.first), log_signal(conn.second));
-                                       cell->unsetPort(conn.first);
+                                       conn.second = SigSpec();
                                }
                        }
                }