interconnect/wishbone: fix Converter case when buses are identical

diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index d32799b6306619774b9d369f2af77a1d75bcce70..1fbdf975981031ab818e3c999870f82eae971f77 100644 (file)
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -486,7 +486,7 @@ class Converter(Module):
             upconverter = UpConverter(master, slave)
             self.submodules += upconverter
         else:
-            master.connect(slave)
+            self.comb += master.connect(slave)
 
 
 class Cache(Module):