fhdl: forbid zero-length signals

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index c2268428d01c3117b9cf7d6e86cad7ebd651ecfd..7ab425456da257c4c9ee8e75f051487efbc752c8 100644 (file)
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -262,7 +262,8 @@ class Signal(Value):
                                self.nbits, self.signed = bits_sign
                        else:
                                self.nbits, self.signed = bits_sign, False
-               assert(isinstance(self.nbits, int))
+               if not isinstance(self.nbits, int) or self.nbits <= 0:
+                       raise ValueError("Signal width must be a strictly positive integer")
                
                self.variable = variable # deprecated
                self.reset = reset