Clean up more memory leaks

--HG--
extra : convert_revision : 32d1b23200752fe5fcdcbafb586f50bbe6db3bf3

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index d8aab0e58e6f702d3f0123cbf7b349a03fafb87c..5c6ab0950ba13593c3b69f2beabe092c36f6285e 100644 (file)
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -583,12 +583,7 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt)
         // Hit
         hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
         // clear dirty bit if write through
-        if (pkt->needsResponse())
-            respond(pkt, curTick+lat);
-        if (pkt->cmd == MemCmd::Writeback) {
-            //Signal that you can kill the pkt/req
-            pkt->flags |= SATISFIED;
-        }
+        respond(pkt, curTick+lat);
         return true;
     }
 
@@ -606,14 +601,14 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt)
     if (pkt->flags & SATISFIED) {
         // happens when a store conditional fails because it missed
         // the cache completely
-        if (pkt->needsResponse())
-            respond(pkt, curTick+lat);
+        respond(pkt, curTick+lat);
     } else {
         missQueue->handleMiss(pkt, size, curTick + hitLatency);
     }
 
-    if (pkt->cmd == MemCmd::Writeback) {
+    if (!pkt->needsResponse()) {
         //Need to clean up the packet on a writeback miss, but leave the request
+        //for the next level.
         delete pkt;
     }