soc: simplify/fix csr busword

diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py
index 132a650f75e4b2b9675b0a4a7401d153d6b22b26..bb454200b52f73d9abfd3eb2104a49d89e29bc55 100644 (file)
--- a/misoclib/soc/__init__.py
+++ b/misoclib/soc/__init__.py
@@ -177,9 +177,9 @@ class SoC(Module):
                                data_width=self.csr_data_width, address_width=self.csr_address_width)
                        self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
                        for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
-                               self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
+                               self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, self.csr_data_width, csrs)
                        for name, memory, mapaddr, mmap in self.csrbankarray.srams:
-                               self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
+                               self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, self.csr_data_width, memory)
 
                # Interrupts
                if hasattr(self.cpu_or_bridge, "interrupt"):