Add DSP_A_MAXWIDTH_PARTIAL, refactor

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index 8e37201e2589f7762f9c678a50d735145581ce59..71d5a54547f5e09dfa644834b214c363bd76720b 100644 (file)
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -27,20 +27,30 @@
  */\r
 \r
 `ifndef DSP_A_MAXWIDTH\r
-$error("Macro DSP_A_MAXWIDTH must be defined");\r
+$fatal(1, "Macro DSP_A_MAXWIDTH must be defined");\r
 `endif\r
 `ifndef DSP_B_MAXWIDTH\r
-$error("Macro DSP_B_MAXWIDTH must be defined");\r
+$fatal(1, "Macro DSP_B_MAXWIDTH must be defined");\r
+`endif\r
+`ifndef DSP_B_MAXWIDTH\r
+$fatal(1, "Macro DSP_B_MAXWIDTH must be defined");\r
+`endif\r
+`ifndef DSP_A_MAXWIDTH_PARTIAL\r
+`define DSP_A_MAXWIDTH_PARTIAL `DSP_A_MAXWIDTH\r
+`endif\r
+`ifndef DSP_B_MAXWIDTH_PARTIAL\r
+`define DSP_B_MAXWIDTH_PARTIAL `DSP_B_MAXWIDTH\r
 `endif\r
 \r
 `ifndef DSP_NAME\r
-$error("Macro DSP_NAME must be defined");\r
+$fatal(1, "Macro DSP_NAME must be defined");\r
 `endif\r
 \r
 `define MAX(a,b) (a > b ? a : b)\r
 `define MIN(a,b) (a < b ? a : b)\r
 \r
-module \$mul (A, B, Y); \r
+(* techmap_celltype = "$mul $__mul" *)\r
+module _80_mul (A, B, Y);\r
        parameter A_SIGNED = 0;\r
        parameter B_SIGNED = 0;\r
        parameter A_WIDTH = 1;\r
@@ -51,12 +61,26 @@ module \$mul (A, B, Y);
        input [B_WIDTH-1:0] B;\r
        output [Y_WIDTH-1:0] Y;\r
 \r
+       parameter _TECHMAP_CELLTYPE_ = "";\r
+\r
        generate\r
-       if (A_SIGNED != B_SIGNED)\r
+       if (0) begin end\r
+`ifdef DSP_A_MINWIDTH\r
+       else if (A_WIDTH < `DSP_A_MINWIDTH)\r
+               wire _TECHMAP_FAIL_ = 1;\r
+`endif\r
+`ifdef DSP_B_MINWIDTH\r
+       else if (B_WIDTH < `DSP_B_MINWIDTH)\r
+               wire _TECHMAP_FAIL_ = 1;\r
+`endif\r
+`ifdef DSP_Y_MINWIDTH\r
+       else if (Y_WIDTH < `DSP_Y_MINWIDTH)\r
+               wire _TECHMAP_FAIL_ = 1;\r
+`endif\r
+       else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED)\r
                wire _TECHMAP_FAIL_ = 1;\r
-       // NB: A_SIGNED == B_SIGNED from here\r
 `ifdef DSP_SIGNEDONLY\r
-       else if (!A_SIGNED)\r
+       else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED)\r
                \$mul #(\r
                        .A_SIGNED(1),\r
                        .B_SIGNED(1),\r
@@ -81,102 +105,53 @@ module \$mul (A, B, Y);
                        .B(A),\r
                        .Y(Y)\r
                );\r
-       else\r
-               \$__mul #(\r
-                       .A_SIGNED(A_SIGNED),\r
-                       .B_SIGNED(B_SIGNED),\r
-                       .A_WIDTH(A_WIDTH),\r
-                       .B_WIDTH(B_WIDTH),\r
-                       .Y_WIDTH(Y_WIDTH)\r
-               ) _TECHMAP_REPLACE_ (\r
-                       .A(A),\r
-                       .B(B),\r
-                       .Y(Y)\r
-               );\r
-       endgenerate\r
-endmodule\r
-\r
-module \$__mul (A, B, Y);\r
-       parameter A_SIGNED = 0;\r
-       parameter B_SIGNED = 0;\r
-       parameter A_WIDTH = 1;\r
-       parameter B_WIDTH = 1;\r
-       parameter Y_WIDTH = 1;\r
-\r
-       input [A_WIDTH-1:0] A;\r
-       input [B_WIDTH-1:0] B;\r
-       output [Y_WIDTH-1:0] Y;\r
-\r
-       wire [1023:0] _TECHMAP_DO_ = "proc; clean";\r
+       else begin\r
+               wire [1023:0] _TECHMAP_DO_ = "proc; clean";\r
 \r
 `ifdef DSP_SIGNEDONLY\r
-       localparam sign_headroom = 1;\r
+               localparam sign_headroom = 1;\r
 `else\r
-       localparam sign_headroom = 0;\r
+               localparam sign_headroom = 0;\r
 `endif\r
 \r
-       genvar i;\r
-       generate\r
-        if (0) begin end\r
-`ifdef DSP_A_MINWIDTH\r
-               else if (A_WIDTH < `DSP_A_MINWIDTH)\r
-                       wire _TECHMAP_FAIL_ = 1;\r
-`endif\r
-`ifdef DSP_B_MINWIDTH\r
-               else if (B_WIDTH < `DSP_B_MINWIDTH)\r
-                       wire _TECHMAP_FAIL_ = 1;\r
-`endif\r
-`ifdef DSP_Y_MINWIDTH\r
-               else if (Y_WIDTH < `DSP_Y_MINWIDTH)\r
-                       wire _TECHMAP_FAIL_ = 1;\r
-`endif\r
-               else if (A_WIDTH > `DSP_A_MAXWIDTH) begin\r
-                       localparam n = (A_WIDTH+`DSP_A_MAXWIDTH-sign_headroom-1) / (`DSP_A_MAXWIDTH-sign_headroom);\r
-                       localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH);\r
-                       localparam last_Y_WIDTH = `MIN(partial_Y_WIDTH, B_WIDTH+A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom));\r
+               genvar i;\r
+               if (A_WIDTH > `DSP_A_MAXWIDTH) begin\r
+                       localparam n = (A_WIDTH-`DSP_A_MAXWIDTH+`DSP_A_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);\r
+                       localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL);\r
+                       localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);\r
+                       localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;\r
                        if (A_SIGNED && B_SIGNED) begin\r
-                               wire signed [partial_Y_WIDTH-1:0] partial [n-2:0];\r
+                               wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];\r
                                wire signed [last_Y_WIDTH-1:0] last_partial;\r
-                               wire signed [Y_WIDTH-1:0] partial_sum [n-1:0];\r
+                               wire signed [Y_WIDTH-1:0] partial_sum [n:0];\r
                        end\r
                        else begin\r
                                wire [partial_Y_WIDTH-1:0] partial [n-1:0];\r
                                wire [last_Y_WIDTH-1:0] last_partial;\r
-                               wire [Y_WIDTH-1:0] partial_sum [n-1:0];\r
+                               wire [Y_WIDTH-1:0] partial_sum [n:0];\r
                        end\r
 \r
-                       \$__mul #(\r
-                               .A_SIGNED(sign_headroom),\r
-                               .B_SIGNED(B_SIGNED),\r
-                               .A_WIDTH(`DSP_A_MAXWIDTH),\r
-                               .B_WIDTH(B_WIDTH),\r
-                               .Y_WIDTH(partial_Y_WIDTH)\r
-                       ) mul_slice_first (\r
-                               .A({{sign_headroom{1'b0}}, A[`DSP_A_MAXWIDTH-sign_headroom-1 : 0]}),\r
-                               .B(B),\r
-                               .Y(partial[0])\r
-                       );\r
-                       assign partial_sum[0] = partial[0];\r
-\r
-                       for (i = 1; i < n-1; i=i+1) begin:slice\r
+                       for (i = 0; i < n; i=i+1) begin:slice\r
                                \$__mul #(\r
                                        .A_SIGNED(sign_headroom),\r
                                        .B_SIGNED(B_SIGNED),\r
-                                       .A_WIDTH(`DSP_A_MAXWIDTH),\r
+                                       .A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL),\r
                                        .B_WIDTH(B_WIDTH),\r
                                        .Y_WIDTH(partial_Y_WIDTH)\r
                                ) mul_slice (\r
-                                       .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH-sign_headroom) +: `DSP_A_MAXWIDTH-sign_headroom]}),\r
+                                       .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}),\r
                                        .B(B),\r
                                        .Y(partial[i])\r
                                );\r
                                // TODO: Currently a 'cascade' approach to summing the partial\r
                                //       products is taken here, but a more efficient 'binary\r
                                //       reduction' approach also exists...\r
-                               assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1];\r
+                               if (i == 0)\r
+                                       assign partial_sum[i] = partial[i];\r
+                               else\r
+                                       assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];\r
                        end\r
 \r
-                       localparam last_A_WIDTH = A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom);\r
                        \$__mul #(\r
                                .A_SIGNED(A_SIGNED),\r
                                .B_SIGNED(B_SIGNED),\r
@@ -188,56 +163,46 @@ module \$__mul (A, B, Y);
                                .B(B),\r
                                .Y(last_partial)\r
                        );\r
-                       assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2];\r
-                       assign Y = partial_sum[n-1];\r
+                       assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];\r
+                       assign Y = partial_sum[n];\r
                end\r
                else if (B_WIDTH > `DSP_B_MAXWIDTH) begin\r
-                       localparam n = (B_WIDTH+`DSP_B_MAXWIDTH-sign_headroom-1) / (`DSP_B_MAXWIDTH-sign_headroom);\r
-                       localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH);\r
-                       localparam last_Y_WIDTH = `MIN(partial_Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom));\r
+                       localparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);\r
+                       localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL);\r
+                       localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);\r
+                       localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;\r
                        if (A_SIGNED && B_SIGNED) begin\r
-                               wire signed [partial_Y_WIDTH-1:0] partial [n-2:0];\r
+                               wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];\r
                                wire signed [last_Y_WIDTH-1:0] last_partial;\r
-                               wire signed [Y_WIDTH-1:0] partial_sum [n-1:0];\r
+                               wire signed [Y_WIDTH-1:0] partial_sum [n:0];\r
                        end\r
                        else begin\r
                                wire [partial_Y_WIDTH-1:0] partial [n-1:0];\r
                                wire [last_Y_WIDTH-1:0] last_partial;\r
-                               wire [Y_WIDTH-1:0] partial_sum [n-1:0];\r
+                               wire [Y_WIDTH-1:0] partial_sum [n:0];\r
                        end\r
 \r
-                       \$__mul #(\r
-                               .A_SIGNED(A_SIGNED),\r
-                               .B_SIGNED(sign_headroom),\r
-                               .A_WIDTH(A_WIDTH),\r
-                               .B_WIDTH(`DSP_B_MAXWIDTH),\r
-                               .Y_WIDTH(partial_Y_WIDTH)\r
-                       ) mul_first (\r
-                               .A(A),\r
-                               .B({{sign_headroom{1'b0}}, B[`DSP_B_MAXWIDTH-sign_headroom-1 : 0]}),\r
-                               .Y(partial[0])\r
-                       );\r
-                       assign partial_sum[0] = partial[0];\r
-\r
-                       for (i = 1; i < n-1; i=i+1) begin:slice\r
+                       for (i = 0; i < n; i=i+1) begin:slice\r
                                \$__mul #(\r
                                        .A_SIGNED(A_SIGNED),\r
                                        .B_SIGNED(sign_headroom),\r
                                        .A_WIDTH(A_WIDTH),\r
-                                       .B_WIDTH(`DSP_B_MAXWIDTH),\r
+                                       .B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL),\r
                                        .Y_WIDTH(partial_Y_WIDTH)\r
                                ) mul (\r
                                        .A(A),\r
-                                       .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}),\r
+                                       .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}),\r
                                        .Y(partial[i])\r
                                );\r
-                               // TODO: Currently a 'cascade' approach to summing the partial \r
+                               // TODO: Currently a 'cascade' approach to summing the partial\r
                                //       products is taken here, but a more efficient 'binary\r
                                //       reduction' approach also exists...\r
-                               assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[i-1];\r
+                               if (i == 0)\r
+                                       assign partial_sum[i] = partial[i];\r
+                               else\r
+                                       assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];\r
                        end\r
 \r
-                       localparam last_B_WIDTH = B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom);\r
                        \$__mul #(\r
                                .A_SIGNED(A_SIGNED),\r
                                .B_SIGNED(B_SIGNED),\r
@@ -249,10 +214,10 @@ module \$__mul (A, B, Y);
                                .B(B[B_WIDTH-1 -: last_B_WIDTH]),\r
                                .Y(last_partial)\r
                        );\r
-                       assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2];\r
-                       assign Y = partial_sum[n-1];\r
+                       assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];\r
+                       assign Y = partial_sum[n];\r
                end\r
-               else begin \r
+               else begin\r
                        if (A_SIGNED)\r
                                wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);\r
                        else\r
@@ -274,11 +239,12 @@ module \$__mul (A, B, Y);
                                .Y(Y)\r
                        );\r
                end\r
+       end\r
        endgenerate\r
 endmodule\r
 \r
-(* techmap_celltype = "$__mul" *)\r
-module $__soft_mul (A, B, Y); \r
+(* techmap_celltype = "$mul $__mul" *)\r
+module _90_soft_mul (A, B, Y);\r
        parameter A_SIGNED = 0;\r
        parameter B_SIGNED = 0;\r
        parameter A_WIDTH = 1;\r
@@ -292,41 +258,41 @@ module $__soft_mul (A, B, Y);
        // Indirection necessary since mapping\r
        //   back to $mul will cause recursion\r
        generate\r
-               if (A_SIGNED && !B_SIGNED)\r
-                       \$__soft__mul #(\r
-                               .A_SIGNED(A_SIGNED),\r
-                               .B_SIGNED(1),\r
-                               .A_WIDTH(A_WIDTH),\r
-                               .B_WIDTH(B_WIDTH+1),\r
-                               .Y_WIDTH(Y_WIDTH)\r
-                       ) _TECHMAP_REPLACE_ (\r
-                               .A(A),\r
-                               .B({1'b0,B}),\r
-                               .Y(Y)\r
-                       );\r
-               else if (!A_SIGNED && B_SIGNED)\r
-                       \$__soft_mul #(\r
-                               .A_SIGNED(1),\r
-                               .B_SIGNED(B_SIGNED),\r
-                               .A_WIDTH(A_WIDTH+1),\r
-                               .B_WIDTH(B_WIDTH),\r
-                               .Y_WIDTH(Y_WIDTH)\r
-                       ) _TECHMAP_REPLACE_ (\r
-                               .A({1'b0,A}),\r
-                               .B(B),\r
-                               .Y(Y)\r
-                       );\r
-               else\r
-                       \$__soft_mul #(\r
-                               .A_SIGNED(A_SIGNED),\r
-                               .B_SIGNED(B_SIGNED),\r
-                               .A_WIDTH(A_WIDTH),\r
-                               .B_WIDTH(B_WIDTH),\r
-                               .Y_WIDTH(Y_WIDTH)\r
-                       ) _TECHMAP_REPLACE_ (\r
-                               .A(A),\r
-                               .B(B),\r
-                               .Y(Y)\r
-                       );\r
+       if (A_SIGNED && !B_SIGNED)\r
+               \$__soft_mul #(\r
+                       .A_SIGNED(A_SIGNED),\r
+                       .B_SIGNED(1),\r
+                       .A_WIDTH(A_WIDTH),\r
+                       .B_WIDTH(B_WIDTH+1),\r
+                       .Y_WIDTH(Y_WIDTH)\r
+               ) _TECHMAP_REPLACE_ (\r
+                       .A(A),\r
+                       .B({1'b0,B}),\r
+                       .Y(Y)\r
+               );\r
+       else if (!A_SIGNED && B_SIGNED)\r
+               \$__soft_mul #(\r
+                       .A_SIGNED(1),\r
+                       .B_SIGNED(B_SIGNED),\r
+                       .A_WIDTH(A_WIDTH+1),\r
+                       .B_WIDTH(B_WIDTH),\r
+                       .Y_WIDTH(Y_WIDTH)\r
+               ) _TECHMAP_REPLACE_ (\r
+                       .A({1'b0,A}),\r
+                       .B(B),\r
+                       .Y(Y)\r
+               );\r
+       else\r
+               \$__soft_mul #(\r
+                       .A_SIGNED(A_SIGNED),\r
+                       .B_SIGNED(B_SIGNED),\r
+                       .A_WIDTH(A_WIDTH),\r
+                       .B_WIDTH(B_WIDTH),\r
+                       .Y_WIDTH(Y_WIDTH)\r
+               ) _TECHMAP_REPLACE_ (\r
+                       .A(A),\r
+                       .B(B),\r
+                       .Y(Y)\r
+               );\r
        endgenerate\r
 endmodule\r

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 265cee6d6826a768d84349a7d33584f0ba176dc1..477b2f6f75ef93172e614295dffdc8f4c9111b1a 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -286,7 +286,7 @@ struct SynthXilinxPass : public ScriptPass
 
                        if (!nodsp || help_mode) {
                                // NB: Xilinx multipliers are signed only
-                               run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
+                               run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
                                run("opt_expr -fine", "                 (skip if '-nodsp')");
                                run("wreduce", "                        (skip if '-nodsp')");
                                run("xilinx_dsp", "                     (skip if '-nodsp')");