Pulse trigger signal rather than continuous trigger in Timeline test

diff --git a/gram/compat.py b/gram/compat.py
index 05a5ade6841379dad65b92e2fffa7da389b9b1ce..9d183ef127aeb353f75894cc22f1544c8065a75a 100644 (file)
--- a/gram/compat.py
+++ b/gram/compat.py
@@ -134,6 +134,7 @@ class TimelineTestCase(unittest.TestCase):
 
             yield timeline.trigger.eq(1)
             yield
+            yield timeline.trigger.eq(0)
 
             for i in range(11+1):
                 yield
@@ -154,6 +155,12 @@ class TimelineTestCase(unittest.TestCase):
                     self.assertFalse((yield sigA))
                     self.assertFalse((yield sigB))
 
+            # Ensure no changes happen once the sequence is done
+            for i in range(100):
+                yield
+                self.assertFalse((yield sigA))
+                self.assertFalse((yield sigB))
+
         sim = Simulator(m)
         with sim.write_vcd("test_compat.vcd"):
             sim.add_clock(1e-6)